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Cronomantic's Projects

a-z80 icon a-z80

An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

async_fifo icon async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

bouffalo_sdk icon bouffalo_sdk

BouffaloSDK is the IOT and MCU software development kit provided by the Bouffalo Lab Team, supports all the series of Bouffalo chips. Also it is the combination of bl_mcu_sdk and bl_iot_sdk

ddr3-tang-primer-20k icon ddr3-tang-primer-20k

DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.

divtiesus icon divtiesus

DivTIESUS is a SD/MMC interface for the ZX Spectrum, compatible with ESXDOS. It is not a clone of Mario Pratto's DivMMC.

drt icon drt

DAAD Reborn Tokenizer

eduzebox icon eduzebox

Uzebox clone with SCART connector (RGB output) and most SMD components

fx68k icon fx68k

FX68K version for FOSS tools

hdmi icon hdmi

Send video/audio over HDMI on an FPGA

j68_cpu icon j68_cpu

Small microcoded 68000 verilog softcore

jsspeccy3 icon jsspeccy3

a ZX Spectrum emulator for the browser (forked to include palettes)

jt12 icon jt12

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

jt89 icon jt89

sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility

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