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dadongshangu / async_fifo Goto Github PK

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

License: MIT License

Verilog 16.31% Tcl 23.15% Forth 0.77% Makefile 3.01% SystemVerilog 56.76%

async-fifo verilog-tb uvm fifo asynchronous verification-code

async_fifo's Introduction

📫 Reach me on mail: [email protected]
📫 Reach me on wechat: ddvalley
🔭 I’m currently working on ASIC logic design. I am also interested in Perl/Python/UVM/Design flow/Design methodology;
🌱 I’m currently learning UVM verification /Python /AI /Ethernet;
⚡ Fun: I would like to take photos and essay writing. And I am one member of Toastmasters Club;
⚡ Blog: https://dadongshangu.github.io/
⚡ Wechat official account on essay: 大东山谷
⚡ Wechat official account on ASIC design: 数字逻辑电路小站
⚡ My photos: Michael's photos

async_fifo's People

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ycyang0508 natu4u polyee13 zzzggy jiahuiwen520 gzd668 touchspeed conquer0505 gl123ing hiiask zzsczz mrdoomsday wenwenhaowan sugiuma kamejoko80

async_fifo's Issues

question

您好，我有一点疑问，想问一下asyncf_down_transaction在asyncf_case1_sequence中是被当作读信号发送给sequencer，需要用约束把他的rinc约束为1吗

Parameters not transferred

In the top module, the sync_r2w and sync_w2r synchronization submodules are not assigned an address bus width. This causes errors when you change the FIFO depth.

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