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aes

Advanced Encryption Standard (AES) SystemVerilog Core

ai-chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

apb_vip

This apb vip is designed for APB2, APB3, APB4 protocols

assertion_rerun

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

async_fifo

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

ava-core

A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)

axi

VIP for AXI Protocol

axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

branch_predictor_ece563

cache-design

Implementation of Cache Simulator with Level 1, Level 2 and Victim Cache.

cache_simulator_ece563

Cache Simulator

cnn_ece564

combinator-uvm

UVM Testbench For SystemVerilog Combinator Implementation

convolution-using-systolic-arrays

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cplus_practice

Comman Practice for C++

cracking-the-coding-interview

Solutions for the book: Cracking the coding interview V4. Written in C++.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

deepbench

Benchmarking Deep Learning operations on different hardware

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

ece720

ece745_lc3_verification

North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog

firesim-nvdla

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

floating-point-mac-verilog

32 - bit floating point Multiplier Accumulator Unit (MAC)

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gpio_agent

General Purpose I/O agent written in UVM

gptpu

DOI version of GPTPU for SC 2021