chipsalliance / aib-phy-hardware Goto Github PK

Hi Team,

I have a question related to dual-rail voltage. From the Table 21 in the AIB 2.0 spec. I understood:

• Gen 1 mode: all Bump work at 0.9V
• Gen 2 mode:
  > TX,RX,NS_FWD_CLK,NS_FWD_CLKB,FS_FWD_CLK, FS_FWD_CLKB run at 0.4V
  > Remain IOs run at 0.9V

However when redundancy is active:

• the NS_RCV_CLK/NS_RCV_CLKB will be run as TX[0] and TX[1]
• the FS_RCV_CLK/FS_RCV_CLKB will be run as RX[0] and RX[1]
  => So it mean the *_RCV_CLK should be work as 0.4V as TX/RX bump. Am I correct?

Regards!
Man Nguyen

AIB2.0 model seems to have some connection mismatches, as follows :

1. In the /v2.0/rev1/rtl/aib_channel.v, line 182 to 186, pin AIB[71] is connected to 2 csrs :

      wire [39:0] csr_shift_rxdat = {AIB[100],AIB[101],AIB[98],AIB[99],AIB[96],AIB[97],AIB[94],AIB[95],AIB[92],AIB[93], 
                                     AIB[90], AIB[91], AIB[88],AIB[89],AIB[86],AIB[87],AIB[84],AIB[85],AIB[82],AIB[81],
                                     AIB[80], AIB[81], AIB[78],AIB[79],AIB[76],AIB[77],AIB[74],AIB[75],AIB[72],**AIB[71]**,
                                     AIB[68], AIB[69], AIB[66],AIB[67],AIB[64],AIB[65],AIB[62],AIB[63],AIB[60],AIB[61]};
      wire        csr_shift_fs_fwd_clk = **AIB[71]**;
   

2. The avmm address is the same for pin we_tx_1 in /v2.0/rev1/rtl/aib_avmm_io_csr.v and pin we_redund_3 /v2.0/rev1/rtl/aib_avmm_adapt_csr.v. Is this as expected ?

    wire	[3:0]  we_tx_1 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}}; --> Line 54 in /v2.0/rev1/rtl/aib_avmm_adapt_csr.v
    wire	[3:0]  we_redund_3 = we & (addr[6:0] == 7'h1c) ? byteenable[3:0] : {4{1'b0}}; --> Line 54 in /v2.0/rev1/rtl/aib_avmm_io_csr.v
   

Exists only in the model https://github.com/chipsalliance/aib-phy-hardware/blob/master/v2.0/rev1/rtl/aib_channel.v#L30 but not driven. Can this be removed?

Hello ,

While doing Synthesis getting non synthesizable consturct code errors in many files.
eg: ./rev2/rtl/v1_master/c3lib/rtl/primitives/c3lib_mtie0_ds.sv:
line no24: @@$display("ERROR : %m : replace this section with user technology cell")

What may be solution for this ?

Please provide details for modification for Synthesis of v1_master.

Rahul

Hello,

I have been running the DCC simulation in v1.0/rev1/how2use/sim_dcc and I do not understand what I am supposed to observe; the README.md promises these two to show how DCC works and correct the 40/60 input duty cycle to a quasi-50/50. Given the test files there should also be a loopback test following the calibration of the DCC, but in fact no xx_dcc_cal_done is set and clk_dcc does not behave as a 50/50 clock at all (see screenshot).

Any hint on what I am missing?

Many thanks in advance.

Capucine

Hi,

I have some question about the testbench in rev1/ndsimslv/ folder.
The first question is how to modify the testbench to let the fpga aib module(slave) sends data and the master aib module receive data and loopback to the fpga aib module side?
The second question is how to cancel the alignment mode. whether it need to change the configuration bits both in the master aib side and slave(fpga) aib side, and in that case how to change the configuration bits.

Sincerely
Zixuan Liu

Hi,
In the spec, Figure 42, it shows

However, in the code, the implement in file rtl/aib_sm.v line 510 is difference.

It should change to "&" instead of "|".

Please help to fix.
Thanks

sl72 should look like sl73 and sl74. Should be:
aliasv xalias_sl72 (
.PLUS(),
.MINUS(s_aib[72])
);
Instead of
aliasv xalias_sl72 (
.PLUS(tie_low),
.MINUS(s_aib[72])
);

Refer to AIB Spec Table 55. Alternate Follower Channel Bump Table. Follower AIB72 is an output, so the emib_ch_m2s1.sv should not connect it.

2: should be tx_transfer_en
23: oad should be load
95: por should be power_on_reset

Carried over from earlier Intel repo

Hello,

There is a race condition in the AIB Spec IP in simulation, specifically in the io_buffer/ioring. I have attached a document outlining the scenarios, error situations, and solution that we found while working with the AIB Spec IP.

Can you please investigate this and provide a solution?

Thanks,
Eric

Spec IP Race Condition.pdf

Hello ,

I am trying to Synthesis V1_master .

I have solved all errors only following error is coming in aib_top.v.

Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory i_test_c3adapt_scan_in. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory i_test_c3adapt_tcb_static_common. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:23: Illegal reference to memory o_test_c3adapt_scan_out. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:212: Illegal reference to memory o_test_c3adapt_scan_out. (VER-253)
Error: /home/eitratest15/aib-phy-hardware-master/rev2/rtl/v1_master/c3aibadapt_wrap/rtl/aib_top.v:212: Illegal reference to memory i_test_c3adapt_scan_in. (VER-253)

Can you provide support to resolve these errors.

Thanks and Regards,

Rahul

In looking at v1.0/rev1/ndsimslv, I noticed that the simulation contains writes to reserved bits in the CSRs during the interface configuration.

For example line 154 of test.sv writes a 0x02780204 to address 0x208. This would set bit 9 to a '1' but looking at open_source_aib_csr.xlsx, bit 9 is a reserved read only bit in that register.

What's the reason for this? Should they simply be ignored in the testbench?

The bump spreadsheet
Stratix 10 Chiplet AIB Profile_v1_0_aib_bump_locations.xlsx
only contains master bump locations. Please add slave interface bump locations.

Carried over from earlier Intel repo.

Hi,

I'm trying to run the ndsimslv testbench, but the o_ehip_init_status become 3'b100 and not 3'b111. I checked and all the signals from s10_slave interface are in done/out_of_reset state (config_done, fs_mac_ready, ns_mac_ready, ns_adapter_rstn, iopad_fs_mac_rdy, iopad_ns_mac_rdy). I also tried both REGISTER_MOD and without it. I went down couple modules and rx_rst_sm_cs transitions 2 states forward but stops (gets to WAIT_REMOTE_RX_DLL_LOCK but doesn't go to WAIT_REMOTE_RX_ALIGN_DONE). Am I missing some other setting? Is there some `force term that I should uncomment? or some cfg_avmm_write that I should uncomment?

I'm actually using cocotb+icarus to run the benchmark, it needed small modification to some logic/wire terms to make it work with the system verilog codes. But I doubt if that's causing any problems, as other signals are working properly and the warnings I get are totally fine. Can you run the modelsim (that's the code that I built the testbench upon) and see if it goes through? If so can you put an example waveform (or a temporarily link to one) for me to compare?

Thanks,
Moein

Hello,

In section 2.2.2.2, there are sections as below:
"Once aligned, the adapter does not need to locate the Mark bit again. This permits the transmit side to stop sending Mark bits and instead use that bit position for data.
Once aligned, if the adapter sees an unexpected 0 or 1 in the Mark bit position, the adapter shall set m_rx_align_done LO."

I have 2 questions:

• How RX side notifies TX side to stop sending Mark bit?
• When TX side stops sending Mark bit, how does RX monitor Mark bit and pull the signal m_rx_align_done to low?

Could you help me please?

AIB2.0 model does not support the receiver-domain transmit clock feature properly. Two fixes are needed to resolve the issue:

1. In the aib_adapt_2doto.v file, assign the net fs_rcv_clk to m_fs_rcv_clk as follows:
   assign m_fs_rcv_clk = fs_rcv_clk;

2. In the aib_channel.v file, line 379, change the index of the iopad_aib array connected to iopad_rxclk net from 57 to 59, as follows:
   .iopad_rxclk(iopad_aib[57]), //iopad_fs_rcv_clk), --> current implementation
   .iopad_rxclk(iopad_aib[59]), //iopad_fs_rcv_clk), --> change needed

I would like to confirm the function of signal m_gen2_mode in the v2.0 model since I cannot find it in the AIB 2.0 spec. Does m_gen2_mode = 0 mean the model work in Gen1 mode in the spec and can compile with AIB 1.0 model? And m_gen2_mode = 1 means the model work in Gen2 mode in the spec and can compile with AIB 2.0 model?

a) power_on_reset input to Leader has a dummy aibcr3_bufx1_top hooked up to VCCL(VCCIO) on both supply inputs. The dummy buffx1 provides ESD protection; the signal goes through a custom level shifter (see item b).

b) power_on_reset input to Leader uses a custom level shifter hooked up to VCCL and VDD. The custom level shifter provides power supply sequencing invariance. See files v2_common/aibcr3aux_lib/rtl/aibcr3aux_top_master.v and v2_common/aibcr3aux_lib/rtl/aibcr3_lvshift_vcc.v. Note that aibcr3aux_top_master output o_por_vccl is a dummy. por_vccl is regenerated from por_vcchssi (aka por_aib_vcchssi) in v2_common/ana/aibcr3_frontend.v

c) device_detect input to Follower goes through an AIB IO cell aibcr3_buffx1_top hooked up to VDD on both supply inputs. Note that Follower has VCCD connected to VCCL. See file ./v2_common/aibcr3aux_lib/rtl/aib_aux_dual.v

e) device_detect output from Leader is from a buffx1 hooked up to VCCL(VCCIO) on both supply inputs. device_detect is set to 1 inside the Leader AIB IO section; the signal does not come from VCCD domain.

Hi Team,

To be continue the confirmation about word marking/assembly flow at #59, I'd like to confirm more my understand about word marking/assembly:

1. There are 2 options:
   -PHY executes word marking/assembly internally.
   => m_rx_align_done is used to inform to MAC know that data alignment is done.
   -MAC executes word marking/assembly by itself.
   => m_rx_align_done is not used. it's because Tx MAC send marking bit through data_in_f
   and Rx MAC receive marking bit through data_out_f and MAC process the alignment by itself.

2. When Tx sends marking bits, other bits shall be zero and are unavailable during this process because data alignment has not done

Thank you in advance for your support.

Best regards,
Tram Pham

Hello,

Can you please clarify the relationships between the specification revisions and the AIB generations?

• v1.0/rev1 contains the RTL describing the specs revision 1.2, i.e. the AIB Gen1 (Plus); but then why does how2use contain a simulation involving the phase compensation fifo, which is not supposed to be implemented in v1.0?
• V1.0/rev2 contains the RTL corresponding to the AIB Gen2; Then why is it the v1.0/rev1 code which was updated more recently?
• What are v2.0/rev1 and rev1.1?

Thanks in advance for your help

Capucine

The v2_slave configuration is slightly different than the master.

cfg_avmm_write addresses are "h2xx"

h208 rx fifo
Bit 27: 0 fifo single width, 1 fifo double width
Bit 0: 0 no swap, 1 rxswap

h210 rx fifo
Bits 2:1: 00 FIFO 1x, 01 FIFO 2x, 11 Register
Bit 0: 0 word alignment disable, for FIFO 1x mode, 1 word alignment enable, for FIFO 2x mode

h218 tx fifo
Bit 23: 0 disable word marking, 1 enable word marking
Bits 22:21: 00 FIFO 1x, 01 FIFO 2x, 11 Register mode
Bit 0: 0 no swap, 1 swap data from MAC to far side

Examples:
2x FIFO Mode
208 0A780204
210 02871F03
218 47A08004

Register mode
208 02780204
210 02871f06
218 47608004

The connectivity in
rev2/rtl/v2_slave/aibadapt_wrap/c3aibadapt_wrap_top_v2s.v
needs to change to daisy chain vs. star distribution of i_osc_clk.

Hi

I want to use this interface in my new project. Does this RTL code have been synthesis before. If it has been synthesis, can you tell me about your synthesis environment and how it is synthesis.

Thanks Zixuan

Hi,
When we test repair with below setting
Set: - Mission mode: TX/RX
- Repair code: 4
- Repair upper: 0 (lower, TX)
We got the issue that TX0 pin could NOT shift down to ns_rcv_clk pin while TX1 pin could shift down to ns_rcv_clkb pin.
The cause is that idata_iopad is sync to ilaunch_clk so it should connect to tx_ilaunch_clk instead of ns_rcv_clk_frmac
Fix suggestion:
in rtl/aib_ioring.v line 1117, 1118, it should change from ns_rcv_clk_frmac to tx_launch_clk as below.

Regards

Table 5 of AIB_Usage_Note_v1_2_2.pdf haserrors with the following two signal names:
fs_adapter_rstn
ns_adapter_rstn
The doc needs to be corrected from *_adapt_rstn to *_adapter_rstn.

Hi,

When do repair of Rx18/19, RX20 data is wrong because the repair shift is not correct.

The issue at v2.0/rev1/rtl/aib_channel.v, line 183

the yellow highlight should be AIB[83] (RX20) instead of AIB[81] (RX18).

Recommend fixing at v2.0/rev1/rtl/aib_channel.v, line 183

Could you check this issue?

Thanks

Hi,

When do repair from Tx0 to ns_rcv_clk, Tx0 is not shifted down to ns_rcv_clk.
I think the cause is from the connection of launch clock of io. It should be from tx_ilaunch_clk instead of ns_rcv_clk_frmac

The issue at v2.0/rev1/rtl/aib_ioring.v , line: 1119, 1120

Recommend fixing at v2.0/rev1/rtl/aib_ioring.v , line: 1119, 1120

This issue was reported at #44 , it is already fixed in v1.0/rev1/rtl/aib_ioring.v but it happens again in v2.0

Could you check this issue?

Thanks,

Hello All,

If anyone had tried to synthesis of the code,please provide details of constraint.

Thanks
Rahul
([email protected])

Hello,

Do you have further information (slides, article...) to provide to explain DCC, DLL FSMs, structure and functioning? I find the comments and the documentation (2 slides in FCCM Workshop 2019) rather imprecise.

Many thanks in advance for you help.

Capucine

The April update of the AIB 2.0 spec clarified the DBI bit positions in a full rate word. For DBI to show up at DDR Tx[39] and TX[19], the DBI bits occupy full_rate_data_in[79], full_rate_data_in[78], full_rate_data_in[39], full_rate_data_in[38].
Please update the 2.0 model to use these full rate and DDR bit positions.

Hi

Does the rtl code can config as SDR mode and pass the "ndsimslv" testbench?

Sincerely
Zixuan Liu

2x FIFO example: Address 218 should be assigned value 67A08004
Register mode example: Address 218 should be assigned value 67608004
We discovered a FIFO timing problem with the example values listed.

The function of this upper byte is not documented.

In file aib-phy-hardware/v2.0/rev1/dv/test/task/agent.sv in task ms_phase_adjust_wrkarnd() and sl_phase_adjust_wrkarnd() and in file aib-phy-hardware/v2.0/rev1/dv/test/test_cases/reg_test.inc line 43 and 52 registers are read from and written to where I cannot find a description anywhere. I found files aib-phy-hardware/docs/aib_csr_for_2_0_v5.xlsx and aib-phy-hardware/docs/open_source_aib_csr.xlsx but there the registers / bits are described as reserved.
It is always for parts where MS_AIB_BCA or SL_AIB_BCA needs to be defined.

See drawings. The emib_m1s2 and emib_m2s2 models need to connect ch0 to ch23 and so on.

run_compile_m1bca is only used to connect a Legacy Leader AIB 1.0 to a BCA AIB2.0 Follower. In this case the BCA AIB2.0 HM is rotated. Physically, Follower AIB2.0 Channel 23 connects to Leader AIB1.0 Channel0 -- therefore M1S2_ROTATE EMIB is needed.

Figure 12. Show as implemented in aib_top_wrapper_v2m.sv.

1. Drop dual_mode_select input and logic boxes.
2. Drop m_power_on_reset_i.
3. Drop m_device_detect and m_device_detect_ovrd.

Figure 13. Show as implemented in aib_top_wrapper.v2s.sv.
4. Change m_power_on_reset_i to m_power_on_reset.
5. "To other AIB reset destinations" needs to come from m_power_on_reset.
6. Drop m_por_ovrd.

See Figure 37 in the AIB 2.0 spec.

If I am a user of the module aib_top_v2m in file aib_top_v2m.v then I should:

1. Connect a wire to the port io_aib_aux74, the port io_aib_aux75 and my C4 bump named mst_device_detect
2. Connect a wire to the port io_aib_aux85, the port io_aib_aux87 and my C4 bump named mst_por

Similarly, If I am a user of the module aib_top_v2s in file aib_top_v2s.v then I should:

1. Connect a wire to the port io_aib_aux74, the port io_aib_aux75 and my C4 bump named slv_device_detect
2. Connect a wire to the port io_aib_aux85, the port io_aib_aux87 and my C4 bump named slv_por

The AIB interface provides IO buffers for these signals. The path to the C4 bump is just wire.

The aibcr3_analog.v model (open source version “v2” ) does not tristate (itx_en_buf=1’b0) unless the drive strength inputs are also zeros (indrv_buf[1:0]=2’b00 and ipdrv_buf[1:0]=2’b00).

A question came in about creating a AIB 2.0 PHY. Which test cases should they run? I suggest:

1. AIB 2.0 Gen1 mode to Agilex
   https://github.com/chipsalliance/aib-phy-hardware/blob/master/v2.0/rev1.1/dv/sims/run_compile_m2s1
   As “test.inc” use rev1/dv/test/test_cases/
   fifo1x_test_slaib1.inc
   fifo2x_test_slaib1.inc

2. AIB 2.0 Gen2 to AIB 2.0 Gen2 rotated
   https://github.com/chipsalliance/aib-phy-hardware/blob/master/v2.0/rev1/dv/sims/run_compile_rotate
   As “test.inc” use rev1/dv/test/test_cases/
   fifo1x_test.inc
   fifo2x_fifo4x_test.inc
   fifo2x_test.inc
   fifo4x_dbi_test.inc
   fifo4x_fslpbk_test.inc
   fifo4x_nslpbk_test.inc
   fifo4x_test.inc
   reg_test.inc

See title

For example in file aib_model_top.v

I am synthesizing aib-phy-hardware-master/rev2/rtl/v2_master/c3aibadapt_wrap/rtl/aib_top_v2m.v and here I am getting error as : The macro 'AIBADAPTWRAPTCB_SCAN_CHAINS_RNG' has not been defined. (VER-913)
It is only present in the Top_module while rest consequent blocks it is not defined and hence it is unable to map the design further and hence getting error as : Can't read 'verilog' file 'aib-phy-hardware-master/rev2/rtl/v2_master/c3aibadapt_wrap/rtl/aib_top_v2m.v'.
No designs were read
Warning: The following synthetic libraries should be added to
the list of link libraries:
'dw_foundation.sldb'. (UISN-26)
'dw_foundation.sldb'. (UISN-26)

Kindly Help with the same asap

The slave equivalent to
7.1.2 Alternate (Master) Channel Bump Map
is missing from the 1.2 spec.

Carried over from earlier intel repo.