aritra1705 Goto Github PK

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

asap7

benchmarks

EPFL logic synthesis benchmarks

cep

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

cep-1

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

course-content-dl

NMA deep learning course

dotfiles

A collection of my personal dotfiles

fpga-fabrics-for-redaction-iccad

freepdk3

gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

gnn-re

GNN-RE datasets for circuit recognition

gnnunlock

hal

HAL – The Hardware Analyzer

hw2vec

i99t

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

lunar_lander_project

netsimile

Implementation of NetSimile anomaly detection algorithm.

omla

openfpga

An Open-source FPGA IP Generator

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opentitan

OpenTitan: Open source silicon root of trust

prga

Open-source FPGA research and prototyping framework.

psat

This is a probabilistic SAT attack tool.

pso

Particle Swarm Optimization (PSO) in C

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

rane

sail_gsc

sky90fd-pdk