ASAP7 PDK

Current Version: 1.7

Instructions for setting-up the PDK

Design Rule Manual

Calibre Decks are not a part of this repository and must be downloaded from this webpage. Scroll down to the bottom of the linked webpage and click on "Download Calibre Decks Now". Use the "calibre" directory thus downloaded to replace the "calibre" directory provided in this Github repository.

Calibre Usage Instructions

If you use the ASAP7 PDK in any published work, then we would appreciate a citation for the following article:

L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric, “ASAP: A 7-nm finFET predictive process design kit,” Microelectronics Journal, vol. 53, pp. 105-115, Jul. 2016.

7.5-track library

Current version: 28

If you use the ASAP7 7.5-track standard cell library in any published work, then we would appreciate a citation for the following article:

V. Vashishtha, M. Vangala and L. T. Clark, "ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper," Proc. ICCAD, pp. 992-998, Nov. 2017.

6-track library

Current version: 26

Library designed by:

Abhilash Gangadhar, Maximilian Siath, Sai Aishwarya Batchu, Sai Charan Rajamani, Sai Varun Krishna Tatipamula, and Lawrence T. Clark.

ASAP7 PDK and libraries have a BSD 3-Clause license.

V. Vashishtha and L. T. Clark, “Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node,” Microelectronics J., 2020.

V. Vashishtha, L. Masand, A. Dosi and L. T. Clark, “Systematic Analysis of the Timing and Power Impact of Pure Lines and Cuts Routing for Multiple Patterning,” Proc. SPIE DTCO, 2017.

V. Vashishtha, L. Masand, A. Dosi, and L. T. Clark, “Design Technology Co-Optimization of Back End of Line Design Rules for a 7 nm Predictive Process Design Kit,” Proc. ISQED, 2017.

V. Vashishtha, M. Vangala, P. Sharma, and L. T. Clark, “Robust 7-nm SRAM Design on a Predictive PDK,” Proc. ISCAS, 2017.

L. T. Clark, V. Vashishtha, D. M. Harris, Samuel Dietrich, and Zunyan Wang, “Design Flows and Collateral for the ASAP7 7nm FinFET Predictive Process Design Kit,” Proc. MSE, 2017.

L. T. Clark and V. Vashishtha, , “Design with sub-10 nm FinFET Technologies,” Presented at CICC, 2017.

ASU:

Prof. Lawrence T. Clark, Vinay Vashishtha

Manoj Vangala, Abhilash Gangadhar, Maximilian Siath, Sai Aishwarya Batchu, Sai Charan Rajamani, Sai Varun Krishna Tatipamula, Ankita Dosi, Lovish Masand, Parshant Rana, Aditya Gujja, Chandarasekaran Ramamurthya

Other students of the EEE598 special topics course that developed the original technology files, example cells, netlisting, DRC and LVS flows:

Alan Sam, Nalim Gupta, Rohit Musalay, Akash Thakare, Srividhya Jambunathan, Ramana Rao Pandeshwar, Jayesh Sohanlal, Chandrakanth Puttaswamygowda, Adesh Namekumar, Varun Kaushik, Sanyogita Singh.

ARM:

Saurabh Sinha, Lucian Shifren, Brian Cline, Greg Yeric

Acknowledgements:

Mentor Graphics: Tarek Ramadan (for excellent DRC and LVS training at ASU).