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RISC-V Tools (ISA Simulator and Tests)
Right now the priv-1.9 branch includes some changes from future privileged specs (priv 1.9.1 according to commits), and some of those changes aren't compatible with priv-1.9 (for example: misa's CSR number changed). Is it possible to keep the priv-1.9 branch as just priv-1.9 and move the priv-1.9.1 work to a separate branch? Tags or releases would work as well for priv-1.9.
I got error messages when I built the riscv-isa-sim on my MacBook.
…
../riscv/devices.h:45:19: error: use of undeclared identifier 'calloc'
data = (char*)calloc(1, size);
…
../riscv/devices.h:50:14: error: use of undeclared identifier 'free'; did you
mean 'freg'?
~mem_t() { free(data); }
…
../riscv/devices.h:47:60: error: no member named 'to_string' in namespace 'std'
throw std::runtime_error("couldn't allocate " + std::to_string(siz...
Here is the patch file to fix this problem.
diff --git a/riscv/devices.h b/riscv/devices.h
index ba344db..59e1e7e 100644
--- a/riscv/devices.h
+++ b/riscv/devices.h
@@ -2,6 +2,8 @@
#define _RISCV_DEVICES_H
#include "decode.h"
+#include <cstdlib>
+#include <string>
#include <map>
#include <vector>
I followed the instructions in risc-v repositories in order to have linux running over Spike.
When trying to boot linux with the following command:
spike +disk=path/to/linux-4.6.2/root.bin path/to/riscv-pk/build/bbl vmlinux
I get "Kernel panic". First interesting error in the output is:
VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6
After some research I found some posts which claim that the block device is not supported anymore and I shouldn't use the +disk argument. Instead I should use initramfs. E.g.:
http://stackoverflow.com/questions/37849574/how-to-rebuild-bbl-with-payload-option
I would be greatful to have instructions of how to use initramfs in order to make linux running over Spike (I'm not a linux-kernel expert).
Also I suggest to update the README.
Thanks
Full output follows:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
vvvvvvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv
rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv
rr vvvvvvvvvvvvvvvvvvvvvv
rr vvvvvvvvvvvvvvvvvvvvvvvv rr
rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr
rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr
rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr
rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr
rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr
rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr
rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr
rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr
INSTRUCTION SETS WANT TO BE FREE
[ 0.000000] Linux version 4.6.2-00048-g9079be6 ([email protected]) (gcc version 6.1.0 (GCC) ) #1 Wed Apr 26 13:54:38 IDT 2017
[ 0.000000] Available physical memory: 2040MB
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000080400000-0x00000000ffbfffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080400000-0x00000000ffbfffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080400000-0x00000000ffbfffff]
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 515100
[ 0.000000] Kernel command line:
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] Sorting __ex_table...
[ 0.000000] Memory: 2054268K/2088960K available (2104K kernel code, 110K rwdata, 428K rodata, 68K init, 218K bss, 34692K reserved, 0K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS:0 nr_irqs:0 0
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191126044627 ns
[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=100000)
[ 0.000000] pid_max: default: 32768 minimum: 301
[ 0.000000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] devtmpfs: initialized
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.000000] NET: Registered protocol family 16
[ 0.000000] vgaarb: loaded
[ 0.000000] clocksource: Switched to clocksource riscv_clocksource
[ 0.000000] NET: Registered protocol family 2
[ 0.000000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.000000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.000000] TCP: Hash tables configured (established 16384 bind 16384)
[ 0.000000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[ 0.000000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[ 0.000000] NET: Registered protocol family 1
[ 0.020000] console [sbi_console0] enabled
[ 0.020000] futex hash table entries: 256 (order: 0, 6144 bytes)
[ 0.020000] workingset: timestamp_bits=61 max_order=19 bucket_order=0
[ 0.030000] jitterentropy: Initialization failed with host not compliant with requirements: 2
[ 0.030000] io scheduler noop registered
[ 0.030000] io scheduler cfq registered (default)
[ 0.040000] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6
[ 0.040000] Please append a correct "root=" boot option; here are the available partitions:
[ 0.040000] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[ 0.040000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.6.2-00048-g9079be6 #1
[ 0.040000] Call Trace:
[ 0.040000] [] walk_stackframe+0x0/0xc8
[ 0.040000] [] panic+0xec/0x20c
[ 0.040000] [] mount_block_root+0x248/0x328
[ 0.040000] [] ksysfs_init+0x10/0x40
[ 0.040000] [] prepare_namespace+0x148/0x198
[ 0.040000] [] kernel_init_freeable+0x1c8/0x200
[ 0.040000] [] rest_init+0x80/0x84
[ 0.040000] [] kernel_init+0x10/0x11c
[ 0.040000] [] rest_init+0x80/0x84
[ 0.040000] [] ret_from_syscall+0x10/0x14
[ 0.040000] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
I think the pk build line should export CC=riscv64-unknown-elf-gcc before invoking the build.
CC=riscv64-unknown-elf-gcc build_project riscv-pk --prefix=$RISCV/riscv64-unknown-elf --host=riscv64-unknown-elf
It got removed in commit 2991201
This option is necessary as the user might want to build the other projects with a custom gcc.
https://travis-ci.org/riscv/riscv-tools/jobs/163194991 failed, with:
make -C debug -f /home/travis/build/riscv/riscv-tools/riscv-tests/build/../debug/Makefile src_dir=/home/travis/build/riscv/riscv-tools/riscv-tests/build/../debug XLEN=64
make[1]: Entering directory `/home/travis/build/riscv/riscv-tools/riscv-tests/build/debug'
/home/travis/build/riscv/riscv-tools/riscv-tests/build/../debug/gdbserver.py --isolate --spike64 --cmd spike \
> spike64.log 2>&1 || (sed s/^/spike64.log:\ / spike64.log && false)
spike64.log: Traceback (most recent call last):
...
spike64.log: OSError: [Errno 2] No such file or directory
spike64.log: Exception AttributeError: AttributeError("'Spike' object has no attribute 'process'",) in <bound method Spike.__del__ of <testlib.Spike object at 0x26443d0>> ignored
make[1]: *** [spike64.log] Error 1
I'm pretty sure this is because spike isn't in the PATH when the test is executed. There are 2 possible solutions I can think of:
Since I have no way of testing changes, I don't think I can productively help more than make this suggestion.
First problem I ran into is that it uses the upper-case march format. Fixed that like this:
--- a/build-rv32ima.sh
+++ b/build-rv32ima.sh
@@ -8,8 +8,8 @@
echo "Starting RISC-V Toolchain build process"
build_project riscv-fesvr --prefix=$RISCV
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=RV32IMA
-build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=RV32IMA
-CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv32-unknown-elf
+build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=rv32ima
+build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv32ima
+cC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv32-unknown-elf
echo -e "\\nRISC-V Toolchain installation completed!"
Then I got the following build error:
...
/usr/bin/install: cannot stat ‘/home/tnewsome/SiFive/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/po/zh_CN.gmo’: No such file or directory
*** This configuration is not supported in the following subdirectories:
zlib target-libquadmath target-libatomic target-libcilkrts target-libitm target-libsanitizer target-libvtv target-libmpx gnattools gotools target-libada target-libgfortran target-libbacktrace target-libgo target-libffi target-zlib target-libjava target-libobjc target-libgomp target-liboffloadmic target-libssp target-boehm-gc
(Any other directories should still work fine.)
configure: WARNING: decimal float is not supported for this target, ignored
libtool: install: warning: remember to run `libtool --finish /opt/riscv/libexec/gcc/riscv32-unknown-elf/6.1.0'
configure: WARNING: decimal float is not supported for this target, ignored
configure: WARNING: fixed-point is not supported for this target, ignored
--with-abi=lp64d is not supported for ISA rv32ima
make[2]: *** [configure-gcc] Error 1
make[1]: *** [all] Error 2
make: *** [stamps/build-gcc-newlib] Error 2
I've successfully built master on Linux however I am having trouble building master on macOS X.
Here is my stamps dir:
ls stamps/
build-binutils-newlib
It's failing on the second step: build-gcc-newlib
mclark@monty:/Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build$ make
rm -rf stamps/build-gcc-newlib build-gcc-newlib
mkdir build-gcc-newlib
cd build-gcc-newlib && /Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/configure \
--target=riscv64-unknown-elf \
--prefix=/opt/riscv/toolchain-master \
--disable-shared \
--disable-threads \
--enable-tls \
--enable-languages=c,c++ \
--with-newlib \
--disable-libmudflap \
--disable-libssp \
--disable-libquadmath \
--disable-libgomp \
--disable-nls \
--disable-soft-float \
--disable-multilib \
/bin/sh: /Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/configure: No such file or directory
make: *** [stamps/build-gcc-newlib] Error 127
I noticed that the subdirectory exists. It's almost as if one of the copy commands is working differently on macOS X has there is an additional subdirectory newlib-gcc/newlib
containing the source instead of newlib-gcc
which is what the Makefile is expecting.
mclark@monty:/Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build$ ls /Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/configure
/Volumes/riscv-toolchain-build-master/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/configure
Any ideas on how to troubleshoot?
I really only need binutils for the latest CSRs so I could perhaps overlay the binutils on top of an older gcc...
I build the complete toolchain before. Last year in December.
I followed the exact same steps, but this time ran into a build error when executing:
$ ./build.sh
`/home/usr/RISCVTools/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/gcc/lto-compress.c:34:18: fatal error: zlib.h: No such file or directory
#include <zlib.h>
compilation terminated.
make[3]: *** [lto-compress.o] Error 1
make[2]: *** [all-gcc] Error 2
make[1]: *** [all] Error 2
make: *** [stamps/build-gcc-newlib] Error 2
`
I searched in the folder for the missing header zlib.h and it's nowhere to find.
Did i miss something?
Ubuntu 16.04
GCC 5.4 and 4.8 (both tried)
I am getting a compile error when building with ./build.sh
.
I am on Ubuntu 16.04. I have tried gcc-4.8 and gcc-5.4.
I have installed the apt-gets in the README. I have also set RISCV and added $RISCV/bin to PATH.
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/_default_fcntl.h:184:0,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/fcntl.h:3,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/fcntl.h:1,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/search/hash_page.c:62:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/search/hash.c:44:0:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-hash_page.o] Error 1
make[6]: *** Waiting for unfinished jobs....
make[6]: *** [lib_a-hash.o] Error 1
Makefile:1922: warning: overriding recipe for target 'lib_a-vfwscanf.o'
Makefile:1624: warning: ignoring old recipe for target 'lib_a-vfwscanf.o'
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/_default_fcntl.h:184:0,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/fcntl.h:3,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/stdio/fdopen.c:60:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-fdopen.o] Error 1
make[6]: *** Waiting for unfinished jobs....
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/locale/ldpart.c:30:0:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-ldpart.o] Error 1
make[6]: *** Waiting for unfinished jobs....
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/_default_fcntl.h:184:0,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/fcntl.h:3,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/fcntl.h:1,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/reent/fcntlr.c:5:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/reent/fstatr.c:6:0:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-fcntlr.o] Error 1
make[6]: *** Waiting for unfinished jobs....
make[6]: *** [lib_a-fstatr.o] Error 1
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/reent/renamer.c:6:0:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/reent/mkdirr.c:47:0:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-mkdirr.o] Error 1
make[6]: *** [lib_a-renamer.o] Error 1
In file included from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/_default_fcntl.h:184:0,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/fcntl.h:3,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/fcntl.h:1,
from /path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/reent/openr.c:5:
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:44:3: error: unknown type name 'blksize_t'
blksize_t st_blksize;
^~~~~~~~~
/path/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/newlib/libc/include/sys/stat.h:46:3: error: unknown type name 'blkcnt_t'
blkcnt_t st_blocks;
^~~~~~~~
make[6]: *** [lib_a-openr.o] Error 1
/bin/bash: line 17: cd: riscv: No such file or directory
cp: cannot stat 'riscv/lib.a': No such file or directory
make[7]: *** [lib.a] Error 1
make[6]: *** [all-recursive] Error 1
/path/rocket-chip/riscv-tools/riscv64-unknown-elf/bin/ar: ../search/lib.a: No such file or directory
/path/rocket-chip/riscv-tools/riscv64-unknown-elf/bin/ar: ../stdio/lib.a: No such file or directory
/path/rocket-chip/riscv-tools/riscv64-unknown-elf/bin/ar: ../locale/lib.a: No such file or directory
/path/rocket-chip/riscv-tools/riscv64-unknown-elf/bin/ar: ../reent/lib.a: No such file or directory
/path/rocket-chip/riscv-tools/riscv64-unknown-elf/bin/ar: ../machine/lib.a: No such file or directory
make[5]: *** [all-recursive] Error 1
make[4]: *** [all-recursive] Error 1
make[3]: *** [all] Error 2
make[2]: *** [all-target-newlib] Error 2
make[1]: *** [all] Error 2
make: *** [stamps/build-gcc-newlib] Error 2
HI Support ,
Could you please help us to install riscV from scratch , I am using Centos 6
Hello,
I'm having these issues building the Linux Kernel:
alpha@alpha-VirtualBox:~/fpga-zynq/rocket-chip/linux-3.14.33$ make ARCH=riscv defconfig
*** Default configuration is based on 'riscv64_spike'
#
# configuration written to .config
#
alpha@alpha-VirtualBox:~/fpga-zynq/rocket-chip/linux-3.14.33$ make -j16 ARCH=riscv
scripts/kconfig/conf --silentoldconfig Kconfig
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CC scripts/mod/empty.o
gcc: error: unrecognized argument in option ‘-mabi=lp64’
gcc: note: valid arguments to ‘-mabi=’ are: ms sysv
gcc: error: unrecognized command line option ‘-mno-save-restore’
gcc: error: unrecognized command line option ‘-mstrict-align’
make[2]: *** [scripts/mod/empty.o] Error 1
make[2]: *** Waiting for unfinished jobs....
CC scripts/mod/devicetable-offsets.s
gcc: error: unrecognized argument in option ‘-mabi=lp64’
gcc: note: valid arguments to ‘-mabi=’ are: ms sysv
gcc: error: unrecognized command line option ‘-mno-save-restore’
gcc: error: unrecognized command line option ‘-mstrict-align’
make[2]: *** [scripts/mod/devicetable-offsets.s] Error 1
make[1]: *** [scripts/mod] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [scripts] Error 2
make: *** Waiting for unfinished jobs....
If you could please tell me what I'm missing or how to fix it, I would very much appreciate it.
Thank you !
[ananya@adk riscv-tools]$ git submodule update --init --recursive
Submodule 'riscv-fesvr' ([email protected]:ucb-bar/riscv-fesvr.git) registered for path 'riscv-fesvr'
Submodule 'riscv-gcc' ([email protected]:ucb-bar/riscv-gcc.git) registered for path 'riscv-gcc'
Submodule 'riscv-isa-sim' ([email protected]:ucb-bar/riscv-isa-sim.git) registered for path 'riscv-isa-sim'
Submodule 'riscv-opcodes' ([email protected]:ucb-bar/riscv-opcodes.git) registered for path 'riscv-opcodes'
Submodule 'riscv-pk' ([email protected]:ucb-bar/riscv-pk.git) registered for path 'riscv-pk'
Submodule 'riscv-tests' ([email protected]:ucb-bar/riscv-tests.git) registered for path 'riscv-tests'
Cloning into 'riscv-fesvr'...
Warning: Permanently added the RSA host key for IP address '192.30.252.130' to the list of known hosts.
Permission denied (publickey).
fatal: Could not read from remote repository.
Please make sure you have the correct access rights
and the repository exists.
Clone of '[email protected]:ucb-bar/riscv-fesvr.git' into submodule path 'riscv-fesvr' failed
Changing the submodule url to https://github.com/ fixes the error.
[ananya@adk riscv-tools]$ cat .git/config
[core]
repositoryformatversion = 0
filemode = true
bare = false
logallrefupdates = true
[remote "origin"]
url = https://github.com/ucb-bar/riscv-tools
fetch = +refs/heads/*:refs/remotes/origin/*
[branch "master"]
remote = origin
merge = refs/heads/master
[submodule "riscv-fesvr"]
url = https://github.com/ucb-bar/riscv-fesvr.git
[submodule "riscv-gcc"]
url = https://github.com/ucb-bar/riscv-gcc.git
[submodule "riscv-isa-sim"]
url = https://github.com/ucb-bar/riscv-isa-sim.git
[submodule "riscv-opcodes"]
url = https://github.com/ucb-bar/riscv-opcodes.git
[submodule "riscv-pk"]
url = https://github.com/ucb-bar/riscv-pk.git
[submodule "riscv-tests"]
url = https://github.com/ucb-bar/riscv-tests.git
[ananya@adk riscv-tools]$ cat .git/modules/riscv-tests/config
[core]
repositoryformatversion = 0
filemode = true
bare = false
logallrefupdates = true
worktree = ../../../riscv-tests
[remote "origin"]
url = https://github.com/ucb-bar/riscv-tests.git
fetch = +refs/heads/*:refs/remotes/origin/*
[branch "master"]
remote = origin
merge = refs/heads/master
[submodule "env"]
url = https://github.com/ucb-bar/riscv-test-env.git
Note: This solution is a backdoor approach since it modifies .git/config directly. There should be a better method.
In the riscv-llvm submodule's current tag has a riscv-clang submodule that still uses ssh. Looks like it has been updated in risc-llvm master, just needs to be bumped up to a newer change.
Build fails with the following output:
Building project riscv-gnu-toolchain
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/sys
info.y: warning: 1 shift/reduce conflict [-Wconflicts-sr]
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/def
parse.y: warning: 27 shift/reduce conflicts [-Wconflicts-sr]
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/rcp
arse.y: warning: 58 shift/reduce conflicts [-Wconflicts-sr]
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/rcp
arse.y: warning: 10 reduce/reduce conflicts [-Wconflicts-rr]
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/mcp
arse.y: warning: 1 shift/reduce conflict [-Wconflicts-sr]
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/ld/deffilep.
y: warning: 76 shift/reduce conflicts [-Wconflicts-sr]
In file included from /mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-bin
utils-gdb/ld/ldlex-wrapper.c:26:0:
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/ld/ldlex.l:
In function ‘yylex’:
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/ld/ldlex.l:4
24:14: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (len > yyleng - 2)
^
configure: WARNING: decimal float is not supported for this target, ignored
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/readline/uti
l.c: In function ‘_rl_tropen’:
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/readline/uti
l.c:520:3: warning: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘__pid_t’ [-Wformat=]
sprintf (fnbuf, "/var/tmp/rltrace.%ld", getpid());
^
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/readline/his
tfile.c: In function ‘history_truncate_file’:
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/readline/his
tfile.c:410:13: warning: ignoring return value of ‘write’, declared with attribute warn_unused_result [-Wunused-result]
write (file, bp, chars_read - (bp - buffer));
^
/mnt/c/Users/jchay/Documents/GitHub/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/sim/riscv/co
nfigure: line 13590: SIM_AC_OPTION_HOSTENDIAN: command not found
It would be nice if it was possible to pass these options to the configure scripts since allow it to use a local installation of newer versions of gmp,mpc and mpfr without root rights.
My system configuration:
3.13.0-24-generic #46-Ubuntu SMP Thu Apr 10 19:08:14 UTC 2014 i686 i686 i686 GNU/Linux.
While installing the tool chain we are getting the errors like
gzip: stdin: unexpected end of file
tar: Unexpected EOF in archive
tar: Unexpected EOF in archive
tar: Error is not recoverable: exiting now
make: *** [src/original-binutils] Error 2
We are a company focus on some mixed-signal sensor product, we are very exciting about RISC-V and plan to customize design an in-house ultra low power RISCV core with some special custom instructions. In this deep embedded IoT application, RV32EMC is the best ISA choice. However when we build the riscv-tools, the error reported that the RV32EMC is not supported now. This is very depressing to us. We believe RISCV is going to be brilliantly in deep embedded IoT domain, hence RV32EMC is very important. So sincerely may I have a question when RV32EMC will be supported in riscv-tool?
I am on Mac OS X El Capitan building riscv-tools. With Clang version:
Apple LLVM version 7.0.2 (clang-700.1.81)
Target: x86_64-apple-darwin15.0.0
Thread model: posix
I have successfully built the tool chain and fesvr-eth, spike, riscv64-unknown-elf-* and such are all created. Then move next to the riscv64-unknown-linux-gnu-gcc build. After long into the build with most of the riscv64-unknown-linux-gnu-* done I got an error in the posix build. It stopped at pread.c compilation as follows:
(echo '#define SYSCALL_NAME pread';
echo '#define SYSCALL_NARGS ';
echo '#define SYSCALL_SYMBOL __libc_pread';
echo '#define SYSCALL_CANCELLABLE 1';
echo '#define SYSCALL_NOERRNO 0';
echo '#define SYSCALL_ERRVAL 0';
echo '#include <syscall-template.S>';
echo 'weak_alias (__libc_pread, __libc_pread64)';
echo 'hidden_weak (__libc_pread64)';
echo 'weak_alias (__libc_pread, __pread)';
echo 'hidden_weak (__pread)';
echo 'weak_alias (__libc_pread, pread)';
echo 'hidden_weak (pread)';
echo 'weak_alias (__libc_pread, __pread64)';
echo 'hidden_weak (__pread64)';
echo 'weak_alias (__libc_pread, pread64)';
echo 'hidden_weak (pread64)';
) | riscv64-unknown-linux-gnu-gcc -m64 -c -I../include -I/Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64/posix -I/Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64 -I../sysdeps/unix/sysv/linux/riscv/rv64 -I../sysdeps/unix/sysv/linux/riscv -I../sysdeps/riscv/nptl -I../sysdeps/unix/sysv/linux/generic -I../sysdeps/unix/sysv/linux/wordsize-64 -I../sysdeps/unix/sysv/linux/include -I../sysdeps/unix/sysv/linux -I../sysdeps/nptl -I../sysdeps/pthread -I../sysdeps/gnu -I../sysdeps/unix/inet -I../sysdeps/unix/sysv -I../sysdeps/unix -I../sysdeps/posix -I../sysdeps/riscv/rv64 -I../sysdeps/ieee754/flt-32 -I../sysdeps/ieee754/dbl-64 -I../sysdeps/riscv/rv64/soft-fp -I../sysdeps/riscv -I../sysdeps/init_array -I../sysdeps/wordsize-64 -I../sysdeps/riscv/fpu -I../sysdeps/ieee754 -I../sysdeps/generic -I.. -I../libio -I. -D_LIBC_REENTRANT -include /Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64/libc-modules.h -DMODULE_NAME=libc -include ../include/libc-symbols.h -DASSEMBLER -g -Werror=undef -o /Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64/posix/pread.o -x assembler-with-cpp - -MD -MP -MF /Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64/posix/pread.o.dt -MT /Users/phdasu/RD/OddPoint/RISC-V/rocket-chip-Clang/riscv-tools/riscv-gnu-toolchain/build-glibc-linux64/posix/pread.o
and came the error message:
../sysdeps/unix/syscall-template.S: Assembler messages:
../sysdeps/unix/syscall-template.S:84: Error: unrecognized opcode pushargs_' ../sysdeps/unix/syscall-template.S:84: Error: unrecognized opcode
popargs_'
Anyone can help? I tried looking for past issues and cannot find this one. I am still new to github so please bear with me if I am wrong.
Thanks!
Hi,
I was trying to integrate the spike test suite into the riscv-tools .travis.yml
, but I noticed that gdb wasn't installed (build log). I also noticed that the riscv-gnu-toolchain Makefile.in uses --disable-gdb
in a few places. What's the status of testing gdb in travis?
More of a question than an issue, is -msoft-float [supposed to be] supported? I get an internal gcc error if I try to use it. I'm sorry if I missed documentation to this effect.
Hi
To help people get going with RISC-V I have containerized most of the stuff in the riscv-tools repo. The container image can be pulled from https://hub.docker.com/r/sbates130272/riscv/ and the underlying dockerfile can be found at https://github.com/sbates130272/docker-riscv.
It would be great to have people do a bit of testing on this before emailing the wider audience via the mailing list. The plan would be to update this container when new "releases" of the riscv-tools repo is done.
Note there are currently a couple of issues. One is that "mount" is not allowed in a Docker contain and the other is you need AUFS support as the image size exceeds 10G. I'd be happy to review PRs against the Dockerfile is people have better options for these issues or want to add more things to the image.
Stephen
./build.sh
riscv toolchain build success
riscv64-unknown-elf-gcc hello.c
spike pk a.out
terminate called after throwing an instance of 'trap_store_access_fault'
Hello team,
I build the riscv-tools from branch bump-gcc in order to build rv32ima variant that i'm working on. Then I tried to build the riscv-tests from instructions, but a error raised during make:
mm.o: na função
.L5':
mm.c:(.text+0x12c): referência indefinida para fma' mm.c:(.text+0x154): referência indefinida para
fma'
mm.c:(.text+0x184): referência indefinida para fma' mm.c:(.text+0x1b8): referência indefinida para
fma'
mm.o: na função .L7': mm.c:(.text+0x260): referência indefinida para
fma'
mm.o:mm.c:(.text+0xd4c): mais referências indefinidas para seguir fma' collect2: error: ld returned 1 exit status /home/aopenna/RISCV/riscv-tools/riscv-tests/benchmarks/mm/bmark.mk:28: recipe for target 'mm.riscv' failed make[1]: *** [mm.riscv] Error 1 make[1]: Leaving directory '/home/aopenna/RISCV/riscv-tools/riscv-tests/benchmarks' Makefile:18: recipe for target 'benchmarks' failed make: *** [benchmarks] Error 2
I imagine that some configuration on configure.ac
could work, since it is related to a missing reference for fma
function present on math.h
included on the mm.c that generate the error. But this is far from my knowlodge on GNU build tools.
Is there a way to tie the installed version of tools with their version on github? If at some time in the past I installed the tools with ./build.sh, can I determine what git commit I used to build them?
If it does exist, it would be a good command for someone to run if they are having problems and we suspect they are using an old version of the tools.
Hi
Great notes here but I noticed that to compile the Linux kernel for RISCV you need the Linux bc tool and that is not installed by default on Ubuntu. So you might want to add it to your list of apt-get install in your READMEs on this repo and some of the submodule repos.
Thanks - Stephen
I haven't triage this yet, but want to bring attention to it. With a clean pull of
commit 95f0b55eac15921f2133630bc6748131d8f1c0af
Author: Yunsup Lee <[email protected]>
Date: Tue Feb 17 14:36:50 2015 -0800
sync up riscv-tools
and a vanilla build on OSX 10.10.3 (CC=gcc-4.8 CXX=g++-4.8 ./build.sh
), my build fails starting with riscv-pk
:
Installing project riscv-gnu-toolchain
Configuring project riscv-pk
Building project riscv-pk
In file included from ../pk/frontend.c:4:0:
../pk/atomic.h: In function 'spinlock_lock_irqsave':
../pk/atomic.h:77:3: warning: implicit declaration of function 'clear_csr' [-Wimplicit-function-declaration]
long flags = clear_csr(status, SR_EI);
^
../pk/atomic.h:77:26: error: 'status' undeclared (first use in this function)
long flags = clear_csr(status, SR_EI);
^
../pk/atomic.h:77:26: note: each undeclared identifier is reported only once for each function it appears in
../pk/atomic.h: In function 'spinlock_unlock_irqrestore':
../pk/atomic.h:85:3: warning: implicit declaration of function 'set_csr' [-Wimplicit-function-declaration]
set_csr(status, flags & SR_EI);
^
../pk/atomic.h:85:11: error: 'status' undeclared (first use in this function)
set_csr(status, flags & SR_EI);
^
../pk/fp.c: In function 'emulate_fp':
../pk/frontend.c: In function 'frontend_syscall':
../pk/frontend.c:26:3: warning: implicit declaration of function 'write_csr' [-Wimplicit-function-declaration]
write_csr(tohost, magic_mem);
^
../pk/frontend.c:26:13: error: 'tohost' undeclared (first use in this function)
write_csr(tohost, magic_mem);
^
../pk/frontend.c:27:3: warning: implicit declaration of function 'swap_csr' [-Wimplicit-function-declaration]
while (swap_csr(fromhost, 0) == 0);
^
...
Other than that, the tools that installed appears to work.
I get this error when i try to run build script:
Building project riscv-isa-sim
../spike_main/disasm.cc: In constructor ‘disassembler_t::disassembler_t(int)’:
../spike_main/disasm.cc:257:1: note: variable tracking size limit exceeded with -fvar-tracking-assignments, retrying without
disassembler_t::disassembler_t(int xlen)
^~~~~~~~~~~~~~
In file included from ../riscv/devices.h:4:0,
from ../riscv/debug_module.h:7,
from ../riscv/debug_module.cc:3:
../riscv/debug_module.cc: In member function ‘bool debug_module_t::dmi_read(unsigned int, uint32_t*)’:
../riscv/decode.h:182:115: error: result of ‘(-2147483648 << 1)’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
~~~~~~~^~~~
../riscv/debug_module.cc:240:20: note: in expansion of macro ‘set_field’
result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
^~~~~~~~~
../riscv/debug_module.cc: In member function ‘bool debug_module_t::dmi_write(unsigned int, uint32_t)’:
../riscv/decode.h:181:84: error: result of ‘(-2147483648 << 1)’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
~~~~~~~^~~~
../riscv/debug_module.cc:436:33: note: in expansion of macro ‘get_field’
dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
^~~~~~~~~
cc1plus: all warnings being treated as errors
Its ubuntu 17.04 64 bit on VirtualBox on Windows 10 64bit. "Funny" thing is that few weeks ago i built this without problems on virtual machine set up with exactly the same ubuntu image i used on this system.
$ cat use_mkdir.c
#include <sys/stat.h>
#include <sys/types.h>
int main() {mkdir("foo", 0777);}
$ riscv-gcc use_mkdir.c -o use_mkdir.rv
/tmp/cc6bcUNJ.o: In function `main':
use_mkdir.c:(.text+0x1c): undefined reference to `mkdir'
collect2: ld returned 1 exit status
I haven't triaged it yet. To be honest, I'm not even sure if we default to glibc or newlib here. This is the current riscv-tools as of this moment.
I've just installed riscv-tools on ubuntu 15.04. In addition to the packages mentioned in README.md, I've also had to apt-get install libtool
. Maybe you want to add it to the list in README.md.
Building the commit checked into rocket-chip 83a3143 with build.sh works fine until you run the isa tests.
$ cd riscv-tests/isa
$ make run
...
[ FAILED ] rv64mi-p-breakpoint.out (tohost = 5)
[ FAILED ] rv32mi-p-breakpoint.out32 (tohost = 5)
This corresponds to the test commented "Make sure writes don't trap"
Hi,
The guide in README.md currently uses make -j
(without a number) in three places. If make
is actually called that way, it will spawn as many concurrent processes as the makefile allows, effectively acting as a fork bomb on larger projects. To avoid this, I'd recommend using a default number of jobs in the examples, e.g. make -j 16
.
I'm trying to simulate multicore RISC-V processor on Spike using a "-p2" flag.
While debugging I do see that two processor_t objects are created.
However according to the following indications it seems that only single core is actually used:
I'm running simple vmlinux with Busybox according to the instructions in the README, and having the following cpuinfo content:
/ # cat /proc/cpuinfo
hart : 0
isa : RV64G
When trying to execute the program below, I see by debugging Spike that all the program's instructions are executed on same processor.
EDIT: Another indication: Following code prints 1:
#include <stdio.h>
#include <unistd.h>
int main (void)
{
int numCPU = sysconf(_SC_NPROCESSORS_ONLN);
printf ("cpu count: %d\n", numCPU);
return 0;
}
Maybe Busybox doesn't utilize by default the two processor? Something else?
As first stage, also executing multithreading on the embedded simulator (without linux) is also applicable. I just don't know how to do that - pthread API is not available on the non-linux compiler and I wonder which threading API does.
The program mentioned above:
#define _GNU_SOURCE
#include<stdio.h>
#include<string.h>
#include<pthread.h>
#include<stdlib.h>
#include<unistd.h>
int threads_count;
cpu_set_t *cpuset;
pthread_t *tid;
int counter;
pthread_mutex_t lock;
void* doSomeThing(void *arg)
{
unsigned long i = 0;
long index = (long)arg;
int err = pthread_setaffinity_np(tid[index], 1, cpuset + index);
//int err = pthread_setaffinity_np(pthread_self(), 1, cpuset + index);
if (err != 0)
printf("\ncan't INTERNALLY set affinity of thread %d: [%s]", index, strerror(err));
printf("\n Job %d started\n", counter);
for(i=0; i<10;i++)
{
pthread_mutex_lock(&lock);
counter++;
pthread_mutex_unlock(&lock);
}
printf("\n Job %d finished\n", counter);
return NULL;
}
int main(char **argv, int argc)
{
int i = 0;
int err;
counter = 0;
threads_count = 6;
cpuset = (cpu_set_t *)malloc(sizeof(cpu_set_t) * threads_count);
if (pthread_mutex_init(&lock, NULL) != 0)
{
printf("\n mutex init failed\n");
return 1;
}
for (i = 0; i < threads_count; ++i)
{
CPU_ZERO(cpuset + i);
CPU_SET(i, cpuset + i);
}
tid = (pthread_t *)malloc(sizeof(pthread_t) * threads_count);
for (i = 0; i < threads_count; ++i)
{
long l = i;
err = pthread_create(tid + i, NULL, &doSomeThing, (void *)l);
if (err != 0)
printf("\ncan't create thread :[%s]", strerror(err));
err = pthread_setaffinity_np(tid[i], 1, cpuset + i);
if (err != 0)
printf("\ncan't set affinity of thread %d: [%s]", i, strerror(err));
}
pthread_join(tid[0], NULL);
pthread_join(tid[1], NULL);
pthread_mutex_destroy(&lock);
free(tid);
free(cpuset);
return 0;
}
Hello,
My linux directory has the following files:
linux-3.14.33$ ls
arch Documentation ipc Makefile README.md System.map
block drivers Kbuild mm root tools
certs firmware Kconfig modules.order samples usr
COPYING fs kernel Module.symvers scripts virt
CREDITS include lib net security vmlinux
crypto init MAINTAINERS README sound vmlinux.o
I cannot find rootfs.cpio with find . | cpio --quiet -o -H newc > linux-3.14.33/rootfs.cpio
Where is supposed to be ?
Can you please help ?
Thank you
Hello,
RDINSTRET allows us to know the number of instruction retired by processor and by thread i thing.
is it a way to know the number of retired instruction by each execution unit ?
for example : BOOM core 3 issues has 6 execution units, i would like to know the number of instruction retired by each execution units (ALU, FP ...) for each thread.
Thank you in advance
Build fails with
Configuring project riscv-gcc
Building project riscv-gcc
/bin/sh: 2: CFLAGS+=-Wno-error=deprecated-declarations: not found
This seems to be an invalid syntax when being processed by the default ubuntu dash shell (which is what gets executed by /bin/sh
) in riscv-gcc/Makefile.in
.
Changing line 30 of Makefile.in
to
SHELL := /bin/bash
Gets the toolchain building (though with lots and lots of warnings - perhaps expected) and a simple spike pk helloworld
test worked.
The links for both linux-build.sh and busybox-riscv.config are both currently broken after the changes to the website. They're both linked under http://riscv.org/install-guides/ at the moment, which is no longer accessible.
Hi
On my system I noticed that to generate the init file correctly as a symbolic link I needed to be in the init folder and then issue the command 'ln -s ../bin/busybox init' rather than the command in the README. Might be worth altering the README to make that step a bit clearer?
Stephen
configure: WARNING: decimal float is not supported for this target, ignored
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/sim/riscv/configure: line 13590: SIM_AC_OPTION_HOSTENDIAN: command not found
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:100:31: error: 'DEFAULT_GENERATE_ELF_STT_COMMON' undeclared here (not in a function)
int flag_use_elf_stt_common = DEFAULT_GENERATE_ELF_STT_COMMON;
^
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c: In function 'print_version_id':
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:229:14: error: 'TARGET_ALIAS' undeclared (first use in this function)
VERSION, TARGET_ALIAS, BFD_VERSION_STRING);
^
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:229:14: note: each undeclared identifier is reported only once for each function it appears in
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c: In function 'parse_args':
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:674:5: error: 'TARGET_ALIAS' undeclared (first use in this function)
TARGET_ALIAS);
^
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:689:44: error: 'TARGET_CANONICAL' undeclared (first use in this function)
fprintf (stderr, _("canonical = %s\n"), TARGET_CANONICAL);
^
/home/jinxin/Projects/riscv/rocket-chip/riscv-tools/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gas/as.c:690:43: error: 'TARGET_CPU' undeclared (first use in this function)
fprintf (stderr, _("cpu-type = %s\n"), TARGET_CPU);
^
make[5]: *** [as.o] Error 1
make[5]: *** Waiting for unfinished jobs....
make[4]: *** [all-recursive] Error 1
make[3]: *** [all] Error 2
make[2]: *** [all-gas] Error 2
make[2]: *** Waiting for unfinished jobs....
configure: WARNING: no enhanced curses library found; disabling TUI
configure: WARNING: expat is missing or unusable; some features may be unavailable.
configure: WARNING: python is missing or unusable; some features may be unavailable.
configure: WARNING: linux/perf_event.h missing or too old; some features may be unavailable.
configure: WARNING: libipt is missing or unusable; some features may be unavailable.
configure: WARNING: babeltrace is missing or unusable; GDB is unable to read CTF data.
make[1]: *** [all] Error 2
make: *** [stamps/build-binutils-newlib] Error 2
so,how to deal with it? thank you sooooo much!
[root@localhost riscv-tools]# ./build.sh
Starting RISC-V Toolchain build process
Removing existing riscv-openocd/build directory
Configuring project riscv-openocd
libtoolize: error: 'build-aux/config.guess' is newer: use '--force' to overwrite
libtoolize: error: 'build-aux/config.sub' is newer: use '--force' to overwrite
Building project riscv-openocd
../../../src/target/riscv/riscv-013.c: In function ‘assert_reset’:
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1158:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1158:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1161:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1161:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c: In function ‘deassert_reset’:
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1186:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1186:15: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c: In function ‘riscv013_halt_current_hart’:
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1700:14: note: in expansion of macro ‘set_field’
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1700:14: note: in expansion of macro ‘set_field’
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1716:14: note: in expansion of macro ‘set_field’
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1716:14: note: in expansion of macro ‘set_field’
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c: In function ‘riscv013_reset_current_hart’:
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1856:13: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1856:13: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1864:13: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: result of ‘-2147483648 << 1’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1864:13: note: in expansion of macro ‘set_field’
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c: In function ‘riscv013_set_autoexec’:
../../../src/target/riscv/riscv-013.c:71:69: error: left shift of negative value [-Werror=shift-negative-value]
#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
^
../../../src/target/riscv/riscv-013.c:1982:21: note: in expansion of macro ‘get_field’
uint32_t aa_aed = get_field(aa, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF);
^~~~~~~~~
../../../src/target/riscv/riscv-013.c:72:85: error: left shift of negative value [-Werror=shift-negative-value]
t_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
^
../../../src/target/riscv/riscv-013.c:1985:8: note: in expansion of macro ‘set_field’
aa = set_field(aa, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF, aa_aed);
^~~~~~~~~
cc1: all warnings being treated as errors
gmake[6]: *** [riscv/riscv-013.lo] Error 1
gmake[5]: *** [all-recursive] Error 1
gmake[4]: *** [all] Error 2
gmake[3]: *** [all-recursive] Error 1
gmake[2]: *** [all] Error 2
gmake[1]: *** [all-recursive] Error 1
gmake: *** [all] Error 2
any help would be appreciated,
thanks
It's not clear how to build this on a Mac (it has worked in the past). Maybe we could
add a blurb to the README.
This is a tracking issue - I'll fix it.
I am trying to create riscv64 toolchain using buildroot.
I used sifive-next branch as a base to my work.
I used binutils-2.28, gcc-7, glibc-riscv-next, Linux-riscv-next (for Linux headers).
I managed to create working toolchain for riscv64 with this commit
However I found 3 issues I worked around and needed to get fixed.
GCC fails to build GLIBC without warning (I add to --disable-werror to configure)
I think that GCC fails to see that size of -1L is same as a pointer.
log is:
../sysdeps/unix/sysv/linux/mmap64.c: In function ‘__mmap64’:
../sysdeps/unix/sysv/linux/mmap64.c:45:12: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
return (void *) INLINE_SYSCALL_ERROR_RETURN_VALUE (EINVAL);
Faild to build stage 1 compiler (aka inital gcc) due to misssing file
log is:
make[3]: *** No rule to make target '../../gcc/testsuite/selftests', needed by 's-selftest'. Stop.
make[3]: *** Waiting for unfinished jobs....
missing kernel file needed by linux headers, add an empty one arch/riscv/include/uapi/asm/setup.h
log is:
scripts/Makefile.headersinst:72: *** Some mandatory headers (setup.h) are missing in arch/riscv/include/uapi/asm. Stop.
scripts/Makefile.headersinst:26: recipe for target 'asm' failed
Note:
Still with this kernel spike is not booting, need to go back to master (4.6.y)
Normal following-the-directions style build - define RISCV, export RISCV in path and as variable, install all Ubuntu Linux dependencies, run build.sh, produces the following:
make[3]: *** No rule to make target '../build-x86_64-unknown-linux-gnu/libcpp/libcpp.a', needed by 'build/genmatch'. Stop.
make[2]: *** [all-gcc] Error 2
make[1]: *** [all] Error 2
make: *** [stamps/build-gcc-newlib] Error 2
Full gory details of output below.
But it seems either the build is expecting libcpp.a was already built or something is wrong in the makefile.
My experience suggests that probably this is a case of an expected environment variable that doesn't exist on my system. Or an expected script that wasn't run.
I hope it isn't a situation where the build is designed so that you mustn't set the RISCV directory to the same path as the location of the build.sh file (i.e. you must build into an entirely different directory from the source)
Starting RISC-V Toolchain build process
Removing existing riscv-fesvr/build directory
Configuring project riscv-fesvr
Building project riscv-fesvr
Installing project riscv-fesvr
mkdir /home/alex_rast/Local_prg/riscv/include
mkdir /home/alex_rast/Local_prg/riscv/include/fesvr
mkdir /home/alex_rast/Local_prg/riscv/lib
mkdir /home/alex_rast/Local_prg/riscv/bin
mkdir /home/alex_rast/Local_prg/riscv/lib/pkgconfig
Configuring project riscv-isa-sim
Building project riscv-isa-sim
Installing project riscv-isa-sim
mkdir /home/alex_rast/Local_prg/riscv/include/spike
u' modifier ignored since
D' is the default (see U') /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/sysinfo.y: warning: 1 shift/reduce conflict [-Wconflicts-sr] In file included from /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/syslex_wrap.c:25:0: syslex.c: In function ‘yy_get_next_buffer’: syslex.c:1226:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_s ^ /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/defparse.y: warning: 27 shift/reduce conflicts [-Wconflicts-sr] /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/rcparse.y: warning: 58 shift/reduce conflicts [-Wconflicts-sr] /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/rcparse.y: warning: 10 reduce/reduce conflicts [-Wconflicts-rr] /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/mcparse.y: warning: 1 shift/reduce conflict [-Wconflicts-sr] /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/doc/binutils.texi:788: warning: @ref node name should not contain
.'.' /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/binutils/doc/binutils.texi:3678: warning: @ref node name should not contain
.'.' In file included from /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/ld/ldlex-wrapper.c:26:0: ldlex.c: In function ‘yy_get_next_buffer’: ldlex.c:3497:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_s ^ configure: WARNING: decimal float is not supported for this target, ignored ar:
u' modifier ignored since D' is the default (see
U').' /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gdb/doc/gdb.texinfo:18884: warning: @ref node name should not contain
.'.' /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/../riscv-binutils-gdb/gdb/doc/python.texi:3748: warning: @ref node name should not contain
.'libtool --finish /home/alex_rast/Local_prg/riscv/libexec/gcc/riscv64-unknown-elf/7.0.1' configure: WARNING: decimal float is not supported for this target, ignored configure: WARNING: fixed-point is not supported for this target, ignored Links are now set up to build a cross-compiler from x86_64-unknown-linux-gnu to riscv64-unknown-elf. /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/expr.c: In function ‘unsigned int cpp_classify_number(cpp_reader*, const cpp_token*, const char**, source_location)’: /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/expr.c:770:18: warning: format not a string literal and no format arguments [-Wformat-security] 0, message); ^ /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/expr.c:773:39: warning: format not a string literal and no format arguments [-Wformat-security] virtual_location, 0, message); ^ /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/macro.c: In function ‘bool create_iso_definition(cpp_reader*, cpp_macro*)’: /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/macro.c:3105:58: warning: format not a string literal and no format arguments [-Wformat-security] cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ^ /home/alex_rast/Local_prg/riscv/riscv-gnu-toolchain/build/src/newlib-gcc/libcpp/macro.c:3118:58: warning: format not a string literal and no format arguments [-Wformat-security] cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); ^ ar:
u' modifier ignored since D' is the default (see
U')u' modifier ignored since
D' is the default (see `U')I wrote a test program in C consisting of an empty main method. When running it with spike and pk, the PC jumps to address fffffffffffffffe and segfaults. After running spike with a commitlog, I've discovered that the problem lies somewhere in the procedure linkage table in the test executable.
Error Message:
z 0000000000000000 ra 0000000000000000 sp 00000000fefffb50 gp 0000000000802f30
tp 0000000000000000 t0 0000000000000000 t1 0000000000000000 t2 00000000008022b0
s0 0000000000000000 s1 0000000000000000 a0 00000000008003e8 a1 0000000000000001
a2 00000000fefffb58 a3 00000000008003f0 a4 0000000000800480 a5 0000000000000000
a6 00000000fefffb50 a7 0000000000000000 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 ffffffffffffffff t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc fffffffffffffffe va 0000000000000000 insn ffffffff sr 8000000000003008
User fetch segfault @ 0xfffffffffffffffe
Commit Log:
0x0000000000002950 (0x10000073)
0x0000000000002950 (0x10000073)
0x00000000008002e0 (0x00003197) x 3 0x00000000008032e0
0x00000000008002e4 (0xc5018193) x 3 0x0000000000802f30
0x00000000008002e8 (0x00050793) x15 0x0000000000000000
0x00000000008002ec (0x00000517) x10 0x00000000008002ec
0x00000000008002f0 (0x0fc50513) x10 0x00000000008003e8
0x00000000008002f4 (0x00013583) x11 0x0000000000000001
0x00000000008002f8 (0x00810613) x12 0x00000000fefffb58
0x00000000008002fc (0xff017113) x 2 0x00000000fefffb50
0x0000000000800300 (0x00000697) x13 0x0000000000800300
0x0000000000800304 (0x0f068693) x13 0x00000000008003f0
0x0000000000800308 (0x00000717) x14 0x0000000000800308
0x000000000080030c (0x17870713) x14 0x0000000000800480
0x0000000000800310 (0x00010813) x16 0x00000000fefffb50
0x0000000000800314 (0xfbdff06f)
0x00000000008002d0 (0x00002317) x 6 0x00000000008022d0
0x00000000008002d4 (0x45033283) x 5 0x00000000008002b0
0x00000000008002d8 (0x00028367) x 6 0x00000000008002dc
0x00000000008002b0 (0x00002397) x 7 0x00000000008022b0
0x00000000008002b4 (0x40530333) x 6 0x000000000000002c
0x00000000008002b8 (0x4603be03) x28 0xffffffffffffffff
0x00000000008002bc (0xfd430313) x 6 0x0000000000000000
0x00000000008002c0 (0x46038293) x 5 0x0000000000802710
0x00000000008002c4 (0x00135313) x 6 0x0000000000000000
0x00000000008002c8 (0x0082b283) x 5 0x0000000000000000
0x00000000008002cc (0x000e0067)
Program disassembly:
test: file format elf64-littleriscv
Disassembly of section .plt:
00000000008002b0 <_PROCEDURE_LINKAGE_TABLE_>:
8002b0: 97 23 00 00 33 03 53 40 03 be 03 46 13 03 43 fd .#[email protected].
8002c0: 93 82 03 46 13 53 13 00 83 b2 82 00 67 00 0e 00 ...F.S......g...
00000000008002d0 <__libc_start_main@plt>:
8002d0: 00002317 auipc t1,0x2
8002d4: 45033283 ld t0,1104(t1) # 802720 <__TMC_END__+0x10>
8002d8: 00028367 jalr t1,t0
8002dc: 00000013 nop
Disassembly of section .text:
00000000008002e0 <_start>:
8002e0: 00003197 auipc gp,0x3
8002e4: c5018193 addi gp,gp,-944 # 802f30 <_gp>
8002e8: 00050793 mv a5,a0
8002ec: 00000517 auipc a0,0x0
8002f0: 0fc50513 addi a0,a0,252 # 8003e8 <main>
8002f4: 00013583 ld a1,0(sp)
8002f8: 00810613 addi a2,sp,8
8002fc: ff017113 andi sp,sp,-16
800300: 00000697 auipc a3,0x0
800304: 0f068693 addi a3,a3,240 # 8003f0 <__libc_csu_init>
800308: 00000717 auipc a4,0x0
80030c: 17870713 addi a4,a4,376 # 800480 <__libc_csu_fini>
800310: 00010813 mv a6,sp
800314: fbdff06f j 8002d0 <__libc_start_main@plt>
During my riscv evaluation I found that I miss some well known projects I am sure will be needed by others too.
Is there a plan to add them to https://github.com/riscv/ ?
And later to maintain and upstream the riscv port?
Thanks
Noam
hello,everyone.
I read a report for RVC(https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.pdf ), then I'd like to use the RVC to do the similar tests. But it is ambiguous for me to how to do those experiments. I get several problems:
the gcc could not generate the RVC code or assemble code automatically. even with the option -march. I don't know if I did something wrong, because there is no guide book.
I could get the RV assemble code, then I add the RVC assemble code to replace the RV assemble code. the assemble file can generate the elf file, but when I got the instruction list with "spike -l pk", it always tells me there are errors:
-exception illegal instruction, it is a div instruction.
-exception trap instruction access fault
firstly I just thought it was my fault because I modified the assemble file manually. But when I try the RV code, it returns the same error.The compiling and simulating options as follow:
- riscv64-unknown-elf-gcc -march=RV64IFDC
- spike --isa=RV64IFDC -l pk
In my virtual machine, it is strange about the supporting instruction sets.
- Compile the code without the F/D sets, there is a assembler message error " Architecture doesn't allow hardfloat ABI"
-Compile the code with M set, there is another assembler message error " Unsupported ISA subset M"
- the RV64IFDC could get through the compile but do not get the correct executable file.
I really get lost……
when I dump the executable file with riscv64-unknown-elf-objdump -d, I could not find the RVC instrucions I added. I guess they are all decoded into RV instructions. Is that ture?
Are there some options or command lines to tell the gcc to get the RVC assemble file automatically instead of modifying the normal RV assemble file manually? from the report I give above, it mentioned a RVC assembler, but I reeeeeeeeealy do not know how it work and, where the assembler is.
If I did something wrong, please tell me and help me to correct them.
So many thanks to any reply.
Hi, I download the riscv-tools, install the tool with --with-xlen=32 option, I can successfully run hello world with [https://github.com//issues/41](issue 41), then I try to compile C code with the specific RV32I ISA, I tried two ways:
1, I try to use compile option -march=RV32I to compile the C code, and then use command: spike --isa=RV32I /path/to/32bit/pk/pk hello. There is no output, but if I change the command to spike --isa=RV32, the output is as expected.
2, I try to install the tool-chain with option --with-arch=I --with-xlen=32, the result is as 1.
Is there anything wrong? How can I only use RV32I isa?
I got below build error, just wondering is REHL4 supported?
Completely no idea on this error, can anyone provide a tip?
Thanks~
214%./build.sh
Starting RISC-V Toolchain build processRemoving existing riscv-fesvr/build directory
Configuring project riscv-fesvr
Building project riscv-fesvr
/tmp/ccb4mrHV.s: Assembler messages:
/tmp/ccb4mrHV.s:693: Error: unknown pseudo-op:.cfi_personality' /tmp/ccb4mrHV.s:694: Error: unknown pseudo-op:
.cfi_lsda'
gmake: *** [elfloader.o] Error 1
I`m trying execute this command ( spike -l bbl vmlinux ), but i got a infinite loop.
core 0: 0x0000000000001000 (0x7ffff297) auipc t0, 0x7ffff
core 0: 0x0000000000001004 (0x00000597) auipc a1, 0x0
core 0: 0x0000000000001008 (0x01c58593) addi a1, a1, 28
core 0: 0x000000000000100c (0xf1402573) csrr a0, mhartid
core 0: 0x0000000000001010 (0x00028067) jr t0
core 0: 0x0000000080000000 (0x1e80006f) j pc + 0x1e8
core 0: 0x00000000800001e8 (0x00000093) li ra, 0
core 0: 0x00000000800001ec (0x00000113) li sp, 0
core 0: 0x00000000800001f0 (0x00000193) li gp, 0
core 0: 0x00000000800001f4 (0x00000213) li tp, 0
core 0: 0x00000000800001f8 (0x00000293) li t0, 0
core 0: 0x00000000800001fc (0x00000313) li t1, 0
core 0: 0x0000000080000200 (0x00000393) li t2, 0
core 0: 0x0000000080000204 (0x00000413) li s0, 0
core 0: 0x0000000080000208 (0x00000493) li s1, 0
core 0: 0x000000008000020c (0x00000613) li a2, 0
core 0: 0x0000000080000210 (0x00000693) li a3, 0
core 0: 0x0000000080000214 (0x00000713) li a4, 0
core 0: 0x0000000080000218 (0x00000793) li a5, 0
core 0: 0x000000008000021c (0x00000813) li a6, 0
core 0: 0x0000000080000220 (0x00000893) li a7, 0
core 0: 0x0000000080000224 (0x00000913) li s2, 0
core 0: 0x0000000080000228 (0x00000993) li s3, 0
core 0: 0x000000008000022c (0x00000a13) li s4, 0
core 0: 0x0000000080000230 (0x00000a93) li s5, 0
core 0: 0x0000000080000234 (0x00000b13) li s6, 0
core 0: 0x0000000080000238 (0x00000b93) li s7, 0
core 0: 0x000000008000023c (0x00000c13) li s8, 0
core 0: 0x0000000080000240 (0x00000c93) li s9, 0
core 0: 0x0000000080000244 (0x00000d13) li s10, 0
core 0: 0x0000000080000248 (0x00000d93) li s11, 0
core 0: 0x000000008000024c (0x00000e13) li t3, 0
core 0: 0x0000000080000250 (0x00000e93) li t4, 0
core 0: 0x0000000080000254 (0x00000f13) li t5, 0
core 0: 0x0000000080000258 (0x00000f93) li t6, 0
core 0: 0x000000008000025c (0x34001073) csrw mscratch, zero
core 0: 0x0000000080000260 (0x00000297) auipc t0, 0x0
core 0: 0x0000000080000264 (0xda428293) addi t0, t0, -604
core 0: 0x0000000080000268 (0x30529073) csrw mtvec, t0
core 0: 0x000000008000026c (0x30502373) csrr t1, mtvec
core 0: 0x0000000080000270 (0x00629063) bne t0, t1, pc + 0
core 0: 0x0000000080000274 (0x0000a117) auipc sp, 0xa
core 0: 0x0000000080000278 (0xc4c10113) addi sp, sp, -948
core 0: 0x000000008000027c (0xf14026f3) csrr a3, mhartid
core 0: 0x0000000080000280 (0x00c69613) slli a2, a3, 12
core 0: 0x0000000080000284 (0x00c10133) add sp, sp, a2
core 0: 0x0000000080000288 (0x00100713) li a4, 1
core 0: 0x000000008000028c (0x00d75733) srl a4, a4, a3
core 0: 0x0000000080000290 (0x00177713) andi a4, a4, 1
core 0: 0x0000000080000294 (0x00070463) beqz a4, pc + 8
core 0: 0x0000000080000298 (0x1410106f) j pc + 0x1940
core 0: 0x0000000080001bd8 (0x00001141) addi sp, sp, -16
core 0: 0x0000000080001bda (0x0000e406) sd ra, 8(sp)
core 0: 0x0000000080001bdc (0x0000e022) sd s0, 0(sp)
core 0: 0x0000000080001bde (0x0000842e) mv s0, a1
core 0: 0x0000000080001be0 (0xe75ff0ef) jal pc - 0x18c
core 0: 0x0000000080001a54 (0x00001141) addi sp, sp, -16
core 0: 0x0000000080001a56 (0x0000e406) sd ra, 8(sp)
core 0: 0x0000000080001a58 (0x00006799) lui a5, 0x6
core 0: 0x0000000080001a5a (0x30079073) csrw mstatus, a5
core 0: 0x0000000080001a5e (0x000057fd) li a5, -1
core 0: 0x0000000080001a60 (0x10679073) csrw scounteren, a5
core 0: 0x0000000080001a64 (0x30679073) csrw mcounteren, a5
core 0: 0x0000000080001a68 (0x30445073) csrwi mie, 8
core 0: 0x0000000080001a6c (0x18005073) csrwi sptbr, 0
core 0: 0x0000000080001a70 (0x300027f3) csrr a5, mstatus
core 0: 0x0000000080001a74 (0x00006719) lui a4, 0x6
core 0: 0x0000000080001a76 (0x00008ff9) and a5, a5, a4
core 0: 0x0000000080001a78 (0x0000c7b9) beqz a5, pc + 78
core 0: 0x0000000080001a7a (0x301026f3) csrr a3, misa
core 0: 0x0000000080001a7e (0x00008aa1) c.andi (args unknown)
core 0: 0x0000000080001a80 (0x00004781) jr a5
core 0: 0x0000000080001a82 (0x10000713) li a4, 256
core 0: 0x0000000080001a86 (0x0000c6d5) beqz a3, pc + 172
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002104 (0xf0050053) fmv.w.x ft0, a0
core 0: 0x0000000080002108 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000210c (0xf00500d3) fmv.w.x ft1, a0
core 0: 0x0000000080002110 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002114 (0xf0050153) fmv.w.x ft2, a0
core 0: 0x0000000080002118 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000211c (0xf00501d3) fmv.w.x ft3, a0
core 0: 0x0000000080002120 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002124 (0xf0050253) fmv.w.x ft4, a0
core 0: 0x0000000080002128 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000212c (0xf00502d3) fmv.w.x ft5, a0
core 0: 0x0000000080002130 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002134 (0xf0050353) fmv.w.x ft6, a0
core 0: 0x0000000080002138 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000213c (0xf00503d3) fmv.w.x ft7, a0
core 0: 0x0000000080002140 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002144 (0xf0050453) fmv.w.x fs0, a0
core 0: 0x0000000080002148 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000214c (0xf00504d3) fmv.w.x fs1, a0
core 0: 0x0000000080002150 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002154 (0xf0050553) fmv.w.x fa0, a0
core 0: 0x0000000080002158 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000215c (0xf00505d3) fmv.w.x fa1, a0
core 0: 0x0000000080002160 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002164 (0xf0050653) fmv.w.x fa2, a0
core 0: 0x0000000080002168 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000216c (0xf00506d3) fmv.w.x fa3, a0
core 0: 0x0000000080002170 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002174 (0xf0050753) fmv.w.x fa4, a0
core 0: 0x0000000080002178 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000217c (0xf00507d3) fmv.w.x fa5, a0
core 0: 0x0000000080002180 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002184 (0xf0050853) fmv.w.x fa6, a0
core 0: 0x0000000080002188 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000218c (0xf00508d3) fmv.w.x fa7, a0
core 0: 0x0000000080002190 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x0000000080002194 (0xf0050953) fmv.w.x fs2, a0
core 0: 0x0000000080002198 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x000000008000219c (0xf00509d3) fmv.w.x fs3, a0
core 0: 0x00000000800021a0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021a4 (0xf0050a53) fmv.w.x fs4, a0
core 0: 0x00000000800021a8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021ac (0xf0050ad3) fmv.w.x fs5, a0
core 0: 0x00000000800021b0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021b4 (0xf0050b53) fmv.w.x fs6, a0
core 0: 0x00000000800021b8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021bc (0xf0050bd3) fmv.w.x fs7, a0
core 0: 0x00000000800021c0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021c4 (0xf0050c53) fmv.w.x fs8, a0
core 0: 0x00000000800021c8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021cc (0xf0050cd3) fmv.w.x fs9, a0
core 0: 0x00000000800021d0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021d4 (0xf0050d53) fmv.w.x fs10, a0
core 0: 0x00000000800021d8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021dc (0xf0050dd3) fmv.w.x fs11, a0
core 0: 0x00000000800021e0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021e4 (0xf0050e53) fmv.w.x ft8, a0
core 0: 0x00000000800021e8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021ec (0xf0050ed3) fmv.w.x ft9, a0
core 0: 0x00000000800021f0 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021f4 (0xf0050f53) fmv.w.x ft10, a0
core 0: 0x00000000800021f8 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a88 (0x00004501) jr a0
core 0: 0x0000000080001a8a (0x00000697) auipc a3, 0x0
core 0: 0x0000000080001a8e (0x000096be) add a3, a3, a5
core 0: 0x0000000080001a90 (0x67a682e7) jalr t0, a3, 1658
core 0: 0x00000000800021fc (0xf0050fd3) fmv.w.x ft11, a0
core 0: 0x0000000080002200 (0x00028067) jr t0
core 0: 0x0000000080001a94 (0x000007a1) addi a5, a5, 8
core 0: 0x0000000080001a96 (0xfee799e3) bne a5, a4, pc - 14
core 0: 0x0000000080001a9a (0x00305073) csrwi fcsr, 0
core 0: 0x0000000080001a9e (0x22200713) li a4, 546
core 0: 0x0000000080001aa2 (0x30371073) csrw mideleg, a4
core 0: 0x0000000080001aa6 (0x000067ad) lui a5, 0xb
core 0: 0x0000000080001aa8 (0x10978793) addi a5, a5, 265
core 0: 0x0000000080001aac (0x30279073) csrw medeleg, a5
core 0: 0x0000000080001ab0 (0x303026f3) csrr a3, mideleg
core 0: 0x0000000080001ab4 (0x04e69d63) bne a3, a4, pc + 90
core 0: 0x0000000080001ab8 (0x30202773) csrr a4, medeleg
core 0: 0x0000000080001abc (0x02f71763) bne a4, a5, pc + 46
core 0: 0x0000000080001ac0 (0x000060a2) ld ra, 8(sp)
core 0: 0x0000000080001ac2 (0x00000141) addi sp, sp, 16
core 0: 0x0000000080001ac4 (0x00008082) mv ra, zero
core 0: 0x0000000080001be4 (0x00004501) jr a0
core 0: 0x0000000080001be6 (0xfbdff0ef) jal pc - 0x44
core 0: 0x0000000080001ba2 (0xf14027f3) csrr a5, mhartid
core 0: 0x0000000080001ba6 (0x40f507b3) sub a5, a0, a5
core 0: 0x0000000080001baa (0x00006505) lui a0, 0x1
core 0: 0x0000000080001bac (0x0000950a) add a0, a0, sp
core 0: 0x0000000080001bae (0x0000777d) lui a4, 0xffffffff
core 0: 0x0000000080001bb0 (0x000007b2) slli a5, 12
core 0: 0x0000000080001bb2 (0x00008d79) and a0, a0, a4
core 0: 0x0000000080001bb4 (0xfc078793) addi a5, a5, -64
core 0: 0x0000000080001bb8 (0x0000953e) add a0, a0, a5
core 0: 0x0000000080001bba (0x00053023) sd zero, 0(a0)
core 0: 0x0000000080001bbe (0x00053423) sd zero, 8(a0)
core 0: 0x0000000080001bc2 (0x00053823) sd zero, 16(a0)
core 0: 0x0000000080001bc6 (0x00053c23) sd zero, 24(a0)
core 0: 0x0000000080001bca (0x02053023) sd zero, 32(a0)
core 0: 0x0000000080001bce (0x02053423) sd zero, 40(a0)
core 0: 0x0000000080001bd2 (0x02053823) sd zero, 48(a0)
core 0: 0x0000000080001bd6 (0x00008082) mv ra, zero
core 0: 0x0000000080001bea (0x00008522) mv a0, s0
core 0: 0x0000000080001bec (0x3e4000ef) jal pc + 0x3e4
core 0: 0x0000000080001fd0 (0x0000715d) addi sp, sp, -80
core 0: 0x0000000080001fd2 (0x00000797) auipc a5, 0x0
core 0: 0x0000000080001fd6 (0xf2478793) addi a5, a5, -220
core 0: 0x0000000080001fda (0x0000ec3e) sd a5, 24(sp)
core 0: 0x0000000080001fdc (0x00000797) auipc a5, 0x0
core 0: 0x0000000080001fe0 (0xf4a78793) addi a5, a5, -182
core 0: 0x0000000080001fe4 (0x0000f03e) sd a5, 32(sp)
core 0: 0x0000000080001fe6 (0x00000797) auipc a5, 0x0
core 0: 0x0000000080001fea (0xf1a78793) addi a5, a5, -230
core 0: 0x0000000080001fee (0x0000f43e) sd a5, 40(sp)
core 0: 0x0000000080001ff0 (0x0000082c) addi s0, sp, 24
core 0: 0x0000000080001ff2 (0x0000003c) addi s0, sp, 8
core 0: 0x0000000080001ff4 (0x0000e486) sd ra, 72(sp)
core 0: 0x0000000080001ff6 (0x0000f802) sd zero, 48(sp)
core 0: 0x0000000080001ff8 (0x0000fc3e) sd a5, 56(sp)
core 0: 0x0000000080001ffa (0x87eff0ef) jal pc - 0xf82
core 0: 0x0000000080001078 (0x00004118) lw a4, 0(a0)
core 0: 0x000000008000107a (0x00ff0637) lui a2, 0xff0
core 0: 0x000000008000107e (0xff010837) lui a6, 0xff010
core 0: 0x0000000080001082 (0x0087579b) srliw a5, a4, 8
core 0: 0x0000000080001086 (0x0ff60613) addi a2, a2, 255
core 0: 0x000000008000108a (0x0087171b) slliw a4, a4, 8
core 0: 0x000000008000108e (0xf0080813) addi a6, a6, -256
core 0: 0x0000000080001092 (0x01077733) and a4, a4, a6
core 0: 0x0000000080001096 (0x00008ff1) and a5, a5, a2
core 0: 0x0000000080001098 (0x00008fd9) or a5, a5, a4
core 0: 0x000000008000109a (0x0107971b) slliw a4, a5, 16
core 0: 0x000000008000109e (0x0107d79b) srliw a5, a5, 16
core 0: 0x00000000800010a2 (0x00008fd9) or a5, a5, a4
core 0: 0x00000000800010a4 (0xd00e0737) lui a4, 0xd00e0
core 0: 0x00000000800010a8 (0x00002781) addiw a5, a5, 0
core 0: 0x00000000800010aa (0xeed70713) addi a4, a4, -275
core 0: 0x00000000800010ae (0x00e78363) beq a5, a4, pc + 6
core 0: 0x00000000800010b4 (0x00004d18) lw a4, 24(a0)
core 0: 0x00000000800010b6 (0x000046c5) li a3, 17
core 0: 0x00000000800010b8 (0x0087179b) slliw a5, a4, 8
core 0: 0x00000000800010bc (0x0087571b) srliw a4, a4, 8
core 0: 0x00000000800010c0 (0x00008f71) and a4, a4, a2
core 0: 0x00000000800010c2 (0x0107f7b3) and a5, a5, a6
core 0: 0x00000000800010c6 (0x00008fd9) or a5, a5, a4
core 0: 0x00000000800010c8 (0x0107971b) slliw a4, a5, 16
core 0: 0x00000000800010cc (0x0107d79b) srliw a5, a5, 16
core 0: 0x00000000800010d0 (0x00008fd9) or a5, a5, a4
core 0: 0x00000000800010d2 (0x00002781) addiw a5, a5, 0
core 0: 0x00000000800010d4 (0xfcf6efe3) bltu a3, a5, pc - 34
core 0: 0x00000000800010d8 (0x0000455c) lw a5, 12(a0)
core 0: 0x00000000800010da (0x00852883) lw a7, 8(a0)
core 0: 0x00000000800010de (0x000086ae) mv a3, a1
core 0: 0x00000000800010e0 (0x0087971b) slliw a4, a5, 8
core 0: 0x00000000800010e4 (0x0087d59b) srliw a1, a5, 8
core 0: 0x00000000800010e8 (0x0088979b) slliw a5, a7, 8
core 0: 0x00000000800010ec (0x0088d89b) srliw a7, a7, 8
core 0: 0x00000000800010f0 (0x01077733) and a4, a4, a6
core 0: 0x00000000800010f4 (0x00008df1) and a1, a1, a2
core 0: 0x00000000800010f6 (0x0107f833) and a6, a5, a6
core 0: 0x00000000800010fa (0x00c8f633) and a2, a7, a2
core 0: 0x00000000800010fe (0x00b767b3) or a5, a4, a1
core 0: 0x0000000080001102 (0x00c86633) or a2, a6, a2
core 0: 0x0000000080001106 (0x0107959b) slliw a1, a5, 16
core 0: 0x000000008000110a (0x0106171b) slliw a4, a2, 16
core 0: 0x000000008000110e (0x0107d79b) srliw a5, a5, 16
core 0: 0x0000000080001112 (0x0106561b) srliw a2, a2, 16
core 0: 0x0000000080001116 (0x00008e59) or a2, a2, a4
core 0: 0x0000000080001118 (0x00008fcd) or a5, a5, a1
core 0: 0x000000008000111a (0x02061713) slli a4, a2, 32
core 0: 0x000000008000111e (0x02079593) slli a1, a5, 32
core 0: 0x0000000080001122 (0x00009181) c.srli (args unknown)
core 0: 0x0000000080001124 (0x00009301) c.srli (args unknown)
core 0: 0x0000000080001126 (0x000095aa) add a1, a1, a0
core 0: 0x0000000080001128 (0x00004601) jr a2
core 0: 0x000000008000112a (0x0000953a) add a0, a0, a4
core 0: 0x000000008000112c (0xa67ff06f) j pc - 0x59a
core 0: 0x0000000080000b92 (0x00004785) li a5, 1
core 0: 0x0000000080000b94 (0x00007131) addi sp, sp, -192
core 0: 0x0000000080000b96 (0x00001782) slli a5, 32
core 0: 0x0000000080000b98 (0x0000f922) sd s0, 176(sp)
core 0: 0x0000000080000b9a (0x0000f526) sd s1, 168(sp)
core 0: 0x0000000080000b9c (0x00000789) addi a5, a5, 2
core 0: 0x0000000080000b9e (0x00ff04b7) lui s1, 0xff0
core 0: 0x0000000080000ba2 (0xff010437) lui s0, 0xff010
core 0: 0x0000000080000ba6 (0x0000f14a) sd s2, 160(sp)
core 0: 0x0000000080000ba8 (0x0000ed4e) sd s3, 152(sp)
core 0: 0x0000000080000baa (0x0000e952) sd s4, 144(sp)
core 0: 0x0000000080000bac (0x0000e556) sd s5, 136(sp)
core 0: 0x0000000080000bae (0x0000e15a) sd s6, 128(sp)
core 0: 0x0000000080000bb0 (0x0000fcde) sd s7, 120(sp)
core 0: 0x0000000080000bb2 (0x0000f8e2) sd s8, 112(sp)
core 0: 0x0000000080000bb4 (0x0000f4e6) sd s9, 104(sp)
core 0: 0x0000000080000bb6 (0x0000f0ea) sd s10, 96(sp)
core 0: 0x0000000080000bb8 (0x0000fd06) sd ra, 184(sp)
core 0: 0x0000000080000bba (0x0000ecee) sd s11, 88(sp)
core 0: 0x0000000080000bbc (0x00008a32) mv s4, a2
core 0: 0x0000000080000bbe (0x00008caa) mv s9, a0
core 0: 0x0000000080000bc0 (0x00008b2e) mv s6, a1
core 0: 0x0000000080000bc2 (0x00008936) mv s2, a3
core 0: 0x0000000080000bc4 (0x0000ec32) sd a2, 24(sp)
core 0: 0x0000000080000bc6 (0x0000f43e) sd a5, 40(sp)
core 0: 0x0000000080000bc8 (0x0000f832) sd a2, 48(sp)
core 0: 0x0000000080000bca (0x00004d01) jr s10
core 0: 0x0000000080000bcc (0x0ff48493) addi s1, s1, 255
core 0: 0x0000000080000bd0 (0xf0040413) addi s0, s0, -256
core 0: 0x0000000080000bd4 (0x00004989) li s3, 2
core 0: 0x0000000080000bd6 (0x00004a8d) li s5, 3
core 0: 0x0000000080000bd8 (0x00005c17) auipc s8, 0x5
core 0: 0x0000000080000bdc (0xe68c0c13) addi s8, s8, -408
core 0: 0x0000000080000be0 (0x00005b97) auipc s7, 0x5
core 0: 0x0000000080000be4 (0xe70b8b93) addi s7, s7, -400
core 0: 0x0000000080000be8 (0x000ca703) lw a4, 0(s9)
core 0: 0x0000000080000bec (0x0087579b) srliw a5, a4, 8
core 0: 0x0000000080000bf0 (0x0087171b) slliw a4, a4, 8
core 0: 0x0000000080000bf4 (0x00008f61) and a4, a4, s0
core 0: 0x0000000080000bf6 (0x00008fe5) and a5, a5, s1
core 0: 0x0000000080000bf8 (0x00008fd9) or a5, a5, a4
core 0: 0x0000000080000bfa (0x0107971b) slliw a4, a5, 16
core 0: 0x0000000080000bfe (0x0107d79b) srliw a5, a5, 16
core 0: 0x0000000080000c02 (0x00008fd9) or a5, a5, a4
core 0: 0x0000000080000c04 (0x00002781) addiw a5, a5, 0
core 0: 0x0000000080000c06 (0x07378d63) beq a5, s3, pc + 122
core 0: 0x0000000080000c0a (0x00f9f963) bgeu s3, a5, pc + 18
core 0: 0x0000000080000c1c (0x00004705) li a4, 1
core 0: 0x0000000080000c1e (0x08e79d63) bne a5, a4, pc + 154
core 0: 0x0000000080000c22 (0x000d1b63) bnez s10, pc + 22
core 0: 0x0000000080000c26 (0x000a0963) beqz s4, pc + 18
core 0: 0x0000000080000c38 (0x00093783) ld a5, 0(s2)
core 0: 0x0000000080000c3c (0x004c8d13) addi s10, s9, 4
core 0: 0x0000000080000c40 (0x0000f06a) sd s10, 32(sp)
core 0: 0x0000000080000c42 (0x18078263) beqz a5, pc + 388
core 0: 0x0000000080000c46 (0x02093583) ld a1, 32(s2)
core 0: 0x0000000080000c4a (0x00000828) addi s0, sp, 24
core 0: 0x0000000080000c4c (0x00009782) add a5, a5, zero
core 0: 0x0000000080001ef6 (0x0000852e) mv a0, a1
core 0: 0x0000000080001ef8 (0x00004641) li a2, 16
core 0: 0x0000000080001efa (0x00004581) jr a1
core 0: 0x0000000080001efc (0x58e0306f) j pc + 0x358e
core 0: 0x000000008000548a (0x00c567b3) or a5, a0, a2
core 0: 0x000000008000548e (0x00008b9d) c.andi (args unknown)
core 0: 0x0000000080005490 (0x0000962a) add a2, a2, a0
core 0: 0x0000000080005492 (0x0ff5f593) andi a1, a1, 255
core 0: 0x0000000080005496 (0x0000cb91) beqz a5, pc + 20
core 0: 0x00000000800054aa (0x00859793) slli a5, a1, 8
core 0: 0x00000000800054ae (0x00008ddd) or a1, a1, a5
core 0: 0x00000000800054b0 (0x01059793) slli a5, a1, 16
core 0: 0x00000000800054b4 (0x00008fcd) or a5, a5, a1
core 0: 0x00000000800054b6 (0x02079593) slli a1, a5, 32
core 0: 0x00000000800054ba (0x00008ddd) or a1, a1, a5
core 0: 0x00000000800054bc (0xfec576e3) bgeu a0, a2, pc - 20
core 0: 0x00000000800054c0 (0x000087aa) mv a5, a0
core 0: 0x00000000800054c2 (0x000007a1) addi a5, a5, 8
core 0: 0x00000000800054c4 (0xfeb7bc23) sd a1, -8(a5)
core 0: 0x00000000800054c8 (0xfec7ede3) bltu a5, a2, pc - 6
core 0: 0x00000000800054c2 (0x000007a1) addi a5, a5, 8
core 0: 0x00000000800054c4 (0xfeb7bc23) sd a1, -8(a5)
core 0: 0x00000000800054c8 (0xfec7ede3) bltu a5, a2, pc - 6
core 0: 0x00000000800054cc (0x00008082) mv ra, zero
core 0: 0x0000000080000c4e (0x00007502) ld a0, 32(sp)
core 0: 0x0000000080000c50 (0x081040ef) jal pc + 0x4880
core 0: 0x00000000800054d0 (0x00054783) lbu a5, 0(a0)
core 0: 0x00000000800054d4 (0x0000872a) mv a4, a0
core 0: 0x00000000800054d6 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054e4 (0x00004501) jr a0
core 0: 0x00000000800054e6 (0x00008082) mv ra, zero
core 0: 0x0000000080000c54 (0x00009971) c.andi (args unknown)
core 0: 0x0000000080000c56 (0x00000521) addi a0, a0, 8
core 0: 0x0000000080000c58 (0x000086ca) mv a3, s2
core 0: 0x0000000080000c5a (0x00000830) addi s0, sp, 24
core 0: 0x0000000080000c5c (0x000085da) mv a1, s6
core 0: 0x0000000080000c5e (0x00009566) add a0, a0, s9
core 0: 0x0000000080000c60 (0xf33ff0ef) jal pc - 0xce
core 0: 0x0000000080000b92 (0x00004785) li a5, 1
core 0: 0x0000000080000b94 (0x00007131) addi sp, sp, -192
core 0: 0x0000000080000b96 (0x00001782) slli a5, 32
core 0: 0x0000000080000b98 (0x0000f922) sd s0, 176(sp)
core 0: 0x0000000080000b9a (0x0000f526) sd s1, 168(sp)
core 0: 0x0000000080000b9c (0x00000789) addi a5, a5, 2
core 0: 0x0000000080000b9e (0x00ff04b7) lui s1, 0xff0
core 0: 0x0000000080000ba2 (0xff010437) lui s0, 0xff010
core 0: 0x0000000080000ba6 (0x0000f14a) sd s2, 160(sp)
core 0: 0x0000000080000ba8 (0x0000ed4e) sd s3, 152(sp)
core 0: 0x0000000080000baa (0x0000e952) sd s4, 144(sp)
core 0: 0x0000000080000bac (0x0000e556) sd s5, 136(sp)
core 0: 0x0000000080000bae (0x0000e15a) sd s6, 128(sp)
core 0: 0x0000000080000bb0 (0x0000fcde) sd s7, 120(sp)
core 0: 0x0000000080000bb2 (0x0000f8e2) sd s8, 112(sp)
core 0: 0x0000000080000bb4 (0x0000f4e6) sd s9, 104(sp)
core 0: 0x0000000080000bb6 (0x0000f0ea) sd s10, 96(sp)
core 0: 0x0000000080000bb8 (0x0000fd06) sd ra, 184(sp)
core 0: 0x0000000080000bba (0x0000ecee) sd s11, 88(sp)
core 0: 0x0000000080000bbc (0x00008a32) mv s4, a2
core 0: 0x0000000080000bbe (0x00008caa) mv s9, a0
core 0: 0x0000000080000bc0 (0x00008b2e) mv s6, a1
core 0: 0x0000000080000bc2 (0x00008936) mv s2, a3
core 0: 0x0000000080000bc4 (0x0000ec32) sd a2, 24(sp)
core 0: 0x0000000080000bc6 (0x0000f43e) sd a5, 40(sp)
core 0: 0x0000000080000bc8 (0x0000f832) sd a2, 48(sp)
core 0: 0x0000000080000bca (0x00004d01) jr s10
core 0: 0x0000000080000bcc (0x0ff48493) addi s1, s1, 255
core 0: 0x0000000080000bd0 (0xf0040413) addi s0, s0, -256
core 0: 0x0000000080000bd4 (0x00004989) li s3, 2
core 0: 0x0000000080000bd6 (0x00004a8d) li s5, 3
core 0: 0x0000000080000bd8 (0x00005c17) auipc s8, 0x5
core 0: 0x0000000080000bdc (0xe68c0c13) addi s8, s8, -408
core 0: 0x0000000080000be0 (0x00005b97) auipc s7, 0x5
core 0: 0x0000000080000be4 (0xe70b8b93) addi s7, s7, -400
core 0: 0x0000000080000be8 (0x000ca703) lw a4, 0(s9)
core 0: 0x0000000080000bec (0x0087579b) srliw a5, a4, 8
core 0: 0x0000000080000bf0 (0x0087171b) slliw a4, a4, 8
core 0: 0x0000000080000bf4 (0x00008f61) and a4, a4, s0
core 0: 0x0000000080000bf6 (0x00008fe5) and a5, a5, s1
core 0: 0x0000000080000bf8 (0x00008fd9) or a5, a5, a4
core 0: 0x0000000080000bfa (0x0107971b) slliw a4, a5, 16
core 0: 0x0000000080000bfe (0x0107d79b) srliw a5, a5, 16
core 0: 0x0000000080000c02 (0x00008fd9) or a5, a5, a4
core 0: 0x0000000080000c04 (0x00002781) addiw a5, a5, 0
core 0: 0x0000000080000c06 (0x07378d63) beq a5, s3, pc + 122
core 0: 0x0000000080000c0a (0x00f9f963) bgeu s3, a5, pc + 18
core 0: 0x0000000080000c0e (0x0d578163) beq a5, s5, pc + 194
core 0: 0x0000000080000cd0 (0x0e0d1d63) bnez s10, pc + 250
core 0: 0x0000000080000cd4 (0x008ca703) lw a4, 8(s9)
core 0: 0x0000000080000cd8 (0x004ca603) lw a2, 4(s9)
core 0: 0x0000000080000cdc (0x00cc8593) addi a1, s9, 12
core 0: 0x0000000080000ce0 (0x0087179b) slliw a5, a4, 8
core 0: 0x0000000080000ce4 (0x0087571b) srliw a4, a4, 8
core 0: 0x0000000080000ce8 (0x00008f65) and a4, a4, s1
core 0: 0x0000000080000cea (0x00008fe1) and a5, a5, s0
core 0: 0x0000000080000cec (0x0086169b) slliw a3, a2, 8
core 0: 0x0000000080000cf0 (0x00008fd9) or a5, a5, a4
core 0: 0x0000000080000cf2 (0x0086561b) srliw a2, a2, 8
core 0: 0x0000000080000cf6 (0x0107971b) slliw a4, a5, 16
core 0: 0x0000000080000cfa (0x00008ee1) and a3, a3, s0
core 0: 0x0000000080000cfc (0x00008e65) and a2, a2, s1
core 0: 0x0000000080000cfe (0x0107d79b) srliw a5, a5, 16
core 0: 0x0000000080000d02 (0x00008ed1) or a3, a3, a2
core 0: 0x0000000080000d04 (0x00008f5d) or a4, a4, a5
core 0: 0x0000000080000d06 (0x01069d9b) slliw s11, a3, 16
core 0: 0x0000000080000d0a (0x00001702) slli a4, 32
core 0: 0x0000000080000d0c (0x0106d69b) srliw a3, a3, 16
core 0: 0x0000000080000d10 (0x00009301) c.srli (args unknown)
core 0: 0x0000000080000d12 (0x00dde6b3) or a3, s11, a3
core 0: 0x0000000080000d16 (0x0000975a) add a4, a4, s6
core 0: 0x0000000080000d18 (0x00068d9b) sext.w s11, a3
core 0: 0x0000000080000d1c (0x0000fc3a) sd a4, 56(sp)
core 0: 0x0000000080000d1e (0x0000c4ee) sw s11, 72(sp)
core 0: 0x0000000080000d20 (0x0000e0ae) sd a1, 64(sp)
core 0: 0x0000000080000d22 (0x040a0e63) beqz s4, pc + 92
core 0: 0x0000000080000d26 (0x0000853a) mv a0, a4
core 0: 0x0000000080000d28 (0x000085e2) mv a1, s8
core 0: 0x0000000080000d2a (0x0000e43a) sd a4, 8(sp)
core 0: 0x0000000080000d2c (0x7bc040ef) jal pc + 0x47bc
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x0000000080005502 (0x00004501) jr a0
core 0: 0x0000000080005504 (0x0000bfed) j pc - 6
core 0: 0x00000000800054fe (0x00009d19) subw a0, a0, a4
core 0: 0x0000000080005500 (0x00008082) mv ra, zero
core 0: 0x0000000080000d30 (0x00006722) ld a4, 8(sp)
core 0: 0x0000000080000d32 (0x0000e10d) bnez a0, pc + 34
core 0: 0x0000000080000d34 (0x00cca683) lw a3, 12(s9)
core 0: 0x0000000080000d38 (0x0086979b) slliw a5, a3, 8
core 0: 0x0000000080000d3c (0x0086d69b) srliw a3, a3, 8
core 0: 0x0000000080000d40 (0x00008ee5) and a3, a3, s1
core 0: 0x0000000080000d42 (0x00008fe1) and a5, a5, s0
core 0: 0x0000000080000d44 (0x00008fd5) or a5, a5, a3
core 0: 0x0000000080000d46 (0x0107969b) slliw a3, a5, 16
core 0: 0x0000000080000d4a (0x0107d79b) srliw a5, a5, 16
core 0: 0x0000000080000d4e (0x00008fd5) or a5, a5, a3
core 0: 0x0000000080000d50 (0x00fa2823) sw a5, 16(s4)
core 0: 0x0000000080000d54 (0x000085de) mv a1, s7
core 0: 0x0000000080000d56 (0x0000853a) mv a0, a4
core 0: 0x0000000080000d58 (0x790040ef) jal pc + 0x4790
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
core 0: 0x00000000800054ea (0xfff54783) lbu a5, -1(a0)
core 0: 0x00000000800054ee (0x00000585) addi a1, a1, 1
core 0: 0x00000000800054f0 (0xfff5c703) lbu a4, -1(a1)
core 0: 0x00000000800054f4 (0x0000c799) beqz a5, pc + 14
core 0: 0x00000000800054f6 (0xfee789e3) beq a5, a4, pc - 14
core 0: 0x00000000800054e8 (0x00000505) addi a0, a0, 1
Hi all,
I am able to compile & run riscv-tools in 64b mode but I am having some trouble with getting 32b applications running. I seem to be able to compile riscv-tools for 32b mode but riscv-tests failed to compilete, see my comment on #39 for more informations.
When I try to run the helloworld application as documented in the README file I get the expected behavior in my 64b environment, but it fails in my 32b environment, see below.
What I have:
64b env:
VER=20160908-master-64b
export PATH=$PATH:/tools/riscv-tools/install/riscv-tools.$VER/bin/
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/tools/riscv-tools/install/riscv-tools.$VER/lib64/:/tools/riscv-tools/install/riscv-tools.$VER/lib/
riscv64-unknown-elf-gcc -o hello64 hello64.c
spike pk hello64
warning: only got 2931818496 bytes of target mem (wanted 4294967296)
Hello world!
32b env:
VER=20160908-master-32b
export PATH=$PATH:/tools/riscv-tools/install/riscv-tools.$VER/bin/
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/tools/riscv-tools/install/riscv-tools.$VER/lib64/:/tools/riscv-tools/install/riscv-tools.$VER/lib/
riscv32-unknown-elf-gcc -o hello32 hello32.c
spike pk hello32
warning: only got 2931818496 bytes of target mem (wanted 4294967296)
terminate called after throwing an instance of 'std::runtime_error'
what(): could not open pk
When I point it to the 32b version of pk I no longer get the "could not open" error above but I just get this (no Hello World!):
spike /tools/riscv-tools/install/riscv-tools.20160908-master-32b/riscv32-unknown-elf/bin/pk hello32
warning: only got 2931818496 bytes of target mem (wanted 4294967296)
Anyone any idea of what could be wrong?
Thanks,
Michael
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