reading registers from gdb kills spike --isa=RV32IM about riscv-isa-sim HOT 4 OPEN

I'll take a look.

from riscv-isa-sim.

As a workaround, you can tell gdb: set arch riscv:rv32

This may be necessary anyway, since I don't think there's a way for gdb to discover the architecture of the target using the gdb protocol. (I'd love to be proven wrong.) At least though I'm going to make spike not crash.

from riscv-isa-sim.

Could gdb ask for the misa csr and change if it's implemented and reports
rv32?
On Fri, Oct 7, 2016 at 8:04 AM Tim Newsome [email protected] wrote:

As a workaround, you can tell gdb: set arch riscv:rv32

This may be necessary anyway, since I don't think there's a way for gdb to
discover the architecture of the target using the gdb protocol. (I'd love
to be proven wrong.) At least though I'm going to make spike not crash.

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from riscv-isa-sim.

Could gdb ask for the misa csr and change if it's implemented and reports rv32?

That's a good idea. I'll take a look, although I'm not hopeful that it'll be easy to implement.

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