Instruction to instruction inconsistency in writing vstart on instructions that require vstart==0 about riscv-isa-sim HOT 5 CLOSED

We had a discussion on this topic on #1570 and concluded that, when there's a require(vstart == 0), we should delete the explicit write of vstart. In #1573, some, but not all, of these were deleted. If you want to finish the job, go for it!

from riscv-isa-sim.

Thanks for the response. Looks like I was slightly behind the most recent master when making this report; I think only vmcompress.vm has this issue still.

However, it utilizes VI_LOOP_END macro, which contains

#define VI_LOOP_END \
  } \
  P.VU.vstart->write(0);

Just wanted to check to see that you are fine removing the call to this macro in vcompress_vm.h and replacing it with a single }. Another option would be to create a subset of this macro but that seems like overkill for this one case, though it could be better in the long run in case VI_LOOP_END ever needs updated.

v_ext_macros.h

#define VI_LOOP_END_BASE \
  }

#define VI_LOOP_END \
  VI_LOOP_END_BASE \
  P.VU.vstart->write(0);

VI_LOOP_END_BASE would only be used in vcompress_vm.h

Thoughts?

from riscv-isa-sim.

The second option seems cleaner to me since it keeps the implementation of vcompress.vm more symmetric. OK with you, too, @jerryz123?

from riscv-isa-sim.

Yes, the second approach seems more future proof for future extensions which will pattern-match off these definitions

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Resolved by #1624

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