illegal instruction trap at vlm.v instr about riscv-isa-sim HOT 5 OPEN

There are two problems here. First, SEW=64 LMUL=1/8 isn't guaranteed to be supported. In general, you can only assume that LMUL can go as low as (SEW / ELEN), or 1 in this case. You can only reliably use LMUL=1/8 for SEW=8 and ELEN >= 64.

The second problem is that vlm uses EEW=8, which means its EMUL (== LMUL / SEW * EEW) is 1/64, which is also illegal.

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Make sense to me, but then I have 2 more questions:

1. Why vadd.vv_mf8_rm0_int64_1_0_vl4 is passing (same config but unmasked)?
2. Then, what should be the legal SEWs and EEWs for LMUL=1/8?

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As I said, SEW=64 LMUL=1/8 isn't guaranteed to be supported. A given implementation might support it. My guess is that vadd.vv_mf8_rm0_int64_1_0_vl4 is not a portable test program; it'll work on some implementations and not on others.

The masked version should fail on any correct implementation because the vlm has EMUL=1/64, which is invalid.

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And what about this test case (vadd.vv_mf8_rm0_int32_0_0_vl8). when lmul=1/8, sew=32 and vlen=8. Is this test scenario is legal or not? Or how we calculate the legal test cases on the basis of lmul and sew?

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You can always check vill field of vtype register after vsetvli.

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