Comments (4)
fd-0 (stdin) is redirected to the ns16550 UART device model, so piping data into spike via stdin will not work.
A fopen
in your target program will work.
from riscv-isa-sim.
Thanks for your reply.
I'm sorry that my question misled you. I don't want to change my test program, in other words, I don't want to use fopen
. How can I pass the contents of a file to my program? Is it possible to achieve this by modifying the shell command(spike /riscv64-linux-gnu/bin/pk a.out < input.txt
)?
from riscv-isa-sim.
No. Passing the contents of a file to your program is best done with fopen.
from riscv-isa-sim.
OK. Thank you again for your reply.
from riscv-isa-sim.
Related Issues (20)
- Vector Widening Integer Multiply-Add Instructions - not working HOT 2
- fatal error: config.h: No such file or directory HOT 8
- assert failed in vectorUnit.cc from 71line. T&vectorUnit_t::elt(reg_t,reg_t,bool)[with T=long unsigned int; reg_t=long unsigned int]: Assertion '(VLEN>>3)/sizeof(T)>0' failed. HOT 3
- issue in counting numbers of instructions HOT 1
- Dynamic CSR read/write mask HOT 2
- What time the spike will support the zjpm extension?
- Legal ISA string option not accepted HOT 4
- SSTC exception behavior HOT 3
- vsetivli yields illegal instruction exception HOT 3
- Spike behaviour: vector register overlap HOT 1
- doubt with vector masking register instruction
- Reading macro RD behave unexpected HOT 1
- Documentation to add an MMIO device as a plugin HOT 1
- sbbusyerror model breaks openOCD HOT 9
- Use input DTB to set all processor + device configurations properly
- spike cache model
- Dependency file in makefile is missing
- Incorrect IRQ priority with LCOF
- Deprecated dcsr.halt HOT 2
- Dose write-only operation to csr_seed trigger illegal instruction exception ? HOT 1
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