Comments (3)
Spike is correctly implementing what the ISA specification requires in these cases.
from riscv-isa-sim.
Spike is correctly implementing what the ISA specification requires in these cases.
Thank you very much for your reply.
We understand that spike complies with the ISA specification, but we want our microarchitecture implementation to have both scalar and vector floating-point move instructions ignore the high 32 bits of the register (that is, neither check whether the high 32 bits of the register are all ones). Therefore, we modify the spike of the vfmv.v.f instruction on our own to ignore whether the register high 32 bits is correct when the sew is 32.
Thank you very much for your reconfirmation.
from riscv-isa-sim.
Of course you are entitled to build a non-conforming implementation!
from riscv-isa-sim.
Related Issues (20)
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- Need assistance for Executing my targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions HOT 5
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- Segmentation Fault when interrupt handled while interrupts are disabled in machine mode HOT 3
- Commit 584f8551 appears to break enabling the virtualization extension. HOT 1
- Zicntr not listed as supported extension HOT 2
- Spike does not implement the functions of VTA and MTA for "Written with 1s" HOT 8
- `fsqrt.s` with zero source register results `NaN` instead of `0` HOT 3
- Illegal Instruction overlap difference between vfwadd_wf and vwadd_wx HOT 1
- How to change vector extension configuration(vlen, elen)? HOT 4
- `fdiv.s` with a dynamic rounding mode set to `REN` on the spike results in a incorrect rounding HOT 1
- `fmv.w.x` is illegal? HOT 3
- Bug Fix Suggestion for v1.1.0 HOT 1
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