Comments (3)
Spike is correctly implementing what the ISA specification requires in these cases.
from riscv-isa-sim.
Spike is correctly implementing what the ISA specification requires in these cases.
Thank you very much for your reply.
We understand that spike complies with the ISA specification, but we want our microarchitecture implementation to have both scalar and vector floating-point move instructions ignore the high 32 bits of the register (that is, neither check whether the high 32 bits of the register are all ones). Therefore, we modify the spike of the vfmv.v.f instruction on our own to ignore whether the register high 32 bits is correct when the sew is 32.
Thank you very much for your reconfirmation.
from riscv-isa-sim.
Of course you are entitled to build a non-conforming implementation!
from riscv-isa-sim.
Related Issues (20)
- `fdiv.s` with a dynamic rounding mode set to `REN` on the spike results in a incorrect rounding HOT 1
- `fmv.w.x` is illegal? HOT 6
- Bug Fix Suggestion for v1.1.0 HOT 1
- Installation Guide for v1.1.0
- SPIKE + PK C++ `iostream` support HOT 2
- Wrong mstatus.[SXL|UXL] for RV64I in M-mode only config HOT 4
- RV32E - exception priority issue HOT 1
- Discrepancy with respect to maskmax field in mcontrol (spec vs spike) HOT 3
- trap instruction page fault error and mode shifting from M-mode to U-mode in spike debug mode
- Logging the value of registers at a certain point during the simulation possible? HOT 1
- RISC-V Standard Spec Trace Support
- VI_LD_INDEX issue HOT 3
- SFENCE.VMA instruction privilege HOT 1
- Ssdbltrp - VS mode double trap check HOT 4
- Building spike with "--with-priv=m" config option renders spike unusable HOT 13
- Default `pmpcfg0 = 0x000000000000001f` and `pmpaddr0 = 0x003fffffffffffff`. HOT 5
- Smdbltrp - VS mode double trap check HOT 2
- Using RISCV FESVR for lockstep verif in C HOT 3
- Clarification on VMSEQ Instruction Behavior (riscv vector spec1.0) HOT 1
- How to forcefully inject the rtl values into spike HOT 1
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