For the vfmv.v.f, fmv.w.x, fmv.x.w instructions, should spike consistently ignore the higher 32 bits when processing single-precision floating-point numbers? about riscv-isa-sim HOT 3 CLOSED

Spike is correctly implementing what the ISA specification requires in these cases.

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Spike is correctly implementing what the ISA specification requires in these cases.

Thank you very much for your reply.
We understand that spike complies with the ISA specification, but we want our microarchitecture implementation to have both scalar and vector floating-point move instructions ignore the high 32 bits of the register (that is, neither check whether the high 32 bits of the register are all ones). Therefore, we modify the spike of the vfmv.v.f instruction on our own to ignore whether the register high 32 bits is correct when the sew is 32.
Thank you very much for your reconfirmation.

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Of course you are entitled to build a non-conforming implementation!

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