Comments (1)
aswaterman
commented on July 19, 2024
The assertion is because of baked-in assumptions that U-mode is either always present or never present. This affects things like the existence of CSR fields (e.g. mstatus.UXL). For some of these fields, Spike doesn't understand the concept of the field being transient.
I think there's going to be a lot of trial-and-error in getting this to work, and verifying that you've gotten it right with respect to all of these fields will be a pain. There isn't a fundamental software-architectural reason that it isn't possible, though.
from riscv-isa-sim.
Related Issues (20)
- Supporting variable XLEN HOT 3
- mseccfg useed and sseed bits cannot be modified when zkr is implemented
- [BUG] Spike incorrectly executes V extension instructions when vsstatus.vs is off and V=1. HOT 3
- frm is illegal value , a vector fp inst raise illegal inst but it still will make vs dirty HOT 1
- For the vfmv.v.f, fmv.w.x, fmv.x.w instructions, should spike consistently ignore the higher 32 bits when processing single-precision floating-point numbers? HOT 3
- mcontrol6.timing bit is set HOT 4
- Counter-intuitive MMIO device arguments behavior HOT 3
- reading mtinst gives illegal instruction exception HOT 1
- Spike setting VTYPE to 0x8000000000000000 for e16 mf8 HOT 1
- How can I read content from a file and use it as input for an ELF file HOT 4
- misa is not printed by the instruction csrrci HOT 1
- satp written with an unsupported MODE should have no effect HOT 7
- mstatus.fs cannot be written as initial HOT 2
- spike doesn't update sepc and stval in virtual address mode HOT 5
- Why misaligned store will raise store/amo access fault at the function store_slow_path? HOT 3
- Zfa extension instruction fcvtmod_w_d behavior conflict with sail model on too large/ too small boundary HOT 2
- Parse Zve/Zvl to determine RVV settings, instead of --varch HOT 2
- Build fails with "error: 'L_tmpnam' was not declared in this scope" HOT 4
- for vl=0 does vfredsum need to make vd[0]=vs1[0]? HOT 1
- Facing Issue running Zvbb RVV Cryptography Instructions HOT 3
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