Comments (1)
Fixed on current
branch
from qucs_s.
Related Issues (20)
- Add system library of Verilog-A defined devices HOT 8
- Pressing "Simulate" opens a blank design window HOT 6
- Math equation/functions syntax used for making Libraries HOT 3
- Capital D not allowed in Edit Subcircuit Properties menu Description Entry HOT 2
- Modify SPICE RCLDQ devices to provide support for microelectronics PDKs HOT 3
- Qucs-S component graphics HOT 2
- Controlled Sources delay functionality missing in ngspice HOT 2
- Switch time controlled HOT 1
- Add integration between Substrate.lib and Transcalc tool HOT 2
- Usage of Verilog-A modules in subckt's HOT 7
- No symbols when searching in search components HOT 1
- Forbid symbol mode for all files except *.sch and *.va HOT 1
- TransformerPS1S2 Issue HOT 11
- Changes to improve usability HOT 11
- Symbol generation from Verilog-A model HOT 4
- Bug in parsing Verilog-A code HOT 7
- XSPICEPS1S2 transformer issues HOT 6
- Implement shortcut manager
- Option to remove redundant information in schematics HOT 10
- Integrate qucsator_rf as Git submodule HOT 1
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