Hi.
I hope someone would be so kind to explain the Veriiog code used in the pin_scan design to me.

I fail to understand how the uart_tx wire becomes connected to the output pads. I suspect it has something to do with the BB statement and the following line:

pads_o <= state_active ? { (NIO){uart_tx} } : 0; // Duplicates the tx-pin to an array of reg's?

Is BB some kind of Macro and where it the documentation for it?

I've been working on documenting my 5A-75E V8.0
I can compile and run pin-scan [1] on the board, after specifying my FPGA has a CABGA256 package. Then all the pins on the LED connectors are driven, and I can check those with a serial to USB converter.

Next I made a .lpf file, and a verilog program to let each outputs blink in an unique pattern [2]. After setting output enable (FPGA pin M4) to 0, I can drive about half of the outputs on the LED connectors. I have not been able to drive these pins:
J1 pin 3
J1 pin 8
J1 pin 12
J1 pin 14
J1 pin 15

J2 pin 3
J2 pin 8
J2 pin 12
J2 pin 14
J2 pin 15
(and a lot more, see top.v [3] for the full list)

What am I missing in my multiblink program?

[1] https://github.com/cdwijs/chubby75/tree/colorlight-75E-V80/5a-75e/pin-scan
[2] https://github.com/cdwijs/chubby75/tree/colorlight-75E-V80/5a-75e/multiblink
[3]https://github.com/cdwijs/chubby75/blob/colorlight-75E-V80/5a-75e/multiblink/top.v#L14

I've got an offer for the board marked as 5A-75E V6.1 - is it compatible and can be programmed with iCEStudio?

And, more general question, where can I find the difference between 6.0, 6.1, 7.1 and 8.0 boards?

From the seller's picture seems this 6.1 board looks exactly as the 7.1

Any advise is very much appreciated

Does anyone have a working SDRAM controller example for the ESMT devices used on V7 hardware? I quickly looked at the 3'rd party LiteX i the repos but it seems like an uncertain way to start there.

I can prepare a design with a CPU and SDRAM but it would be good to define the I/Os we want to use for serial. Do you have any preference?

Not an issue but documentthe replacement of 74HC245 with SN74CBT3245A for INPUT pins

Reference Links :

Tweet URL : https://twitter.com/claude1079/status/1231194849350647808

Input Test : https://github.com/kittennbfive/5A-75B-tools/tree/master/I_want_inputs

Desoldering https://zeromips.org/posts/2022-05-29-5a-75b/

*** Be sure you add a diode to drop the 5V input voltage to drop the voltag to 4.3V

Part Number : SN74CBT3245APW

You should swap out U28 , that will give you INPUT pins for J1 ( R0, G0, B0, R1, G1, B1 ) and J2 ( R0, G0 )

8 pins should be a good start.

You can test the input pins iusing the above links ( https://github.com/kittennbfive/5A-75B-tools/) or create a flow in Ice Studio (
https://github.com/FPGAwars/icestudio/wiki )

I did a bit of beeping-out of J25, the 20-pin unpopulated 0.1inch header between the ethernet magnetics and the ethernet connectors. Unsurprisingly, it duplicates the rj45 connectors, and does nothing else, so I'm not going to put any more effort then I already have into it, but here's what I've got so far. Note the equals signs: because the magnetics connect two pins with a low-resistance (at DC) connection, I'd need something more complicated then a multimeter to figure out which of those two rj45 pins is connected to which of the two j25 pins.

   J25 / J24B / J24A
   1   / 1=2  / 
   2   / 1=2  / 
   3   / 3=6  / 
   4   / 3=6  / 
   5   / 4=5  / 
   6   / 4=5  / 
   7   / 7=8  / 
   8   / 7=8  / 
   9   / shld / 
   10  / shld / 
   11  /      / shld
   12  /      / shld
   13  /      / 1=2
   14  /      / 1=2
   15  /      / 3=6
   16  /      / 3=6
   17  /      / 4=5
   18  /      / 4=5
   19  /      / 7=8
   20  /      / 7=8

Just installed ISE 14.7 and LiteX as described here. I can successfully build the blink example in ISE and configure the FPGA. But when trying to build sdram_test.py, I get following error:

litex/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/bin/ld: bios.elf section `.rodata' will not fit in region `rom'
litex/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/bin/ld: region `rom' overflowed by 840 bytes
collect2: error: ld returned 1 exit status


and when trying to build rgmii_test.py

Elaborating module <PLL_ADV(BANDWIDTH="OPTIMIZED",CLKFBOUT_MULT=6'b100101,CLKFBOUT_PHASE=0.0,CLKIN1_PERIOD=40.0,CLKIN2_PERIOD=0.0,CLKOUT0_DIVIDE=3'b111,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT0_PHASE=0.0,CLK_FEEDBACK="CLKFBOUT",COMPENSATION="INTERNAL",DIVCLK_DIVIDE=1'b1,REF_JITTER=0.01,SIM_DEVICE="SPARTAN6")>.
ERROR:HDLCompiler:267 - "/home/user/fpga/chubby75/rv901t/build/gateware/platform.v" Line 5398: Cannot find port PWRDWN on this module

Has anyone an idea of what I am doing wrong?

In https://zeromips.org/posts/2022-05-29-5a-75b I have documented my modification of the 5a-75b board. I suppose this could be helpful/encouraging for others. As this github repo is the de facto standard documentation, maybe you could add a link to my post here.

I would like to create gateware that shows what ball of the FPGA goes to what point on the headers.

On each pin, I would like to output a train of pulses, that indicate the ball. First a preamble, and then 2 burst indicating the row and column That way I can look at an LED to figure out the connection.

For example:
A2: 10101010101010000010000010010000 (and then repeat)
G4: 10101010101010000010010010010010010010000010010010010000
C4: 10101010101010000010010010000010010010010000

Has this already been done?
What is the best way to proceed?

Any idea where i can find the datasheet for the ethernet phy Broadcom B50612D used on this board?

I traced the schematic of the button next to JP2 and S1 :

That schematic feels weird, maybe I've made a huge mistake ? What do you think ?

Also, I noticed that P4 from the FPGA isn't connected to the button but rather to U600:B7.

Hi,

I noticed that on my v7.0 hw there are 2 winbond (W9816G6JH-6) sdram chips instead of 2 ESMT M12L16161A-5T.
Besides from that my board looks exactly like the one on the pictures.

Should we add this to the documentation?

Hello,

thanks a lot @miek@ @smunaut for the reverve, i've been using the reversed pinout to prepare LiteX-Boards support (litex-hub/litex-boards@1d9e349) and have a few comment/questions:

V6.1: @smunaut
SDRAM: D9 is listed twice, DQ[7] is probably a typo, is it D8?
Gigabit PHYs: maybe you should add the XTALO frequency: 25MHz and that it can be used as the main FPGA clock.
Have you been able to document the led and button? (sorry i can't do it since i have a V7.0)

V7.0: @miek
For the Gigabit PHYs 0: P5 is listed twice: RXC and ~RESET.
Similar to v6.1:

• the input clock (P6)) is also from one of the XTALO of the Gigabit PHYs and is 25MHz.
• the SDRAM ~CS/~LDQM/~UDQM are connected to GND and CKE connnected to 3v3.

Florent

I ordered some colorlight 5A-75E and got one with V6.0.

The Chips used:

• 1x LFE5U-25F 6BG381C
• 1x 25Q16CSIG Flash
• 2x EM636165TS-6G RAM
• 2x 850612D Ethernet
• 20x VHC245 3600097

I have not used it so far, so no pinout. And they might no longer be made so not sure how imported this is.

Hi colleagues,

I tested the mounting of the JTAG connector glued in the edge of the board, but I found that this configuration is not so "solid" from the mechanical point of view. Also, the JTAG connector in line requires use the color JTAG cable, which it needs to be wired pin by pin in the correct order.

After some quick tests, I found that is possible use the 10-pin JP3 connector, in a way that the standard 14-pin flat cable found in the ultra-low-cost "xinglinx" JTAG adapter can be directly used:

Of course, although the pin numbers are labelled wrong (JTAG pin 1 connected to PCB pin 9, JTAG pin 2 connected to PCB pin 2, etc until all ten first pins are connected), the pin order from JP3 in the PCB is exactly the same as the first 10 pins from the 14-pin JTAG connector, which make it very quick and practical to connect:

VREF(9) TMS(7) TCK(5) TDO(3) TDI(1)
GND(10) NC(8) NC(6) 5V(4) NC(2)

VREF(1) TMS(3) TCK(5) TDO(7) TDI(9) NC(11) HALT(13)
GND(2) GND(4) GND(6) GND(8) GND(10) GND(12) GND(14)

The NC pins are not connected in the PCB and can be connected to the JTAG GND, but the 5V(4) is powered by the +5V in the PCB, which means that is better bender or cut this pin in a way that is not physically connected to the flat cable, in order to avoid a short circuit in the JTAG adapter between the GND and 5V!

Well, in the other side of the board, the main advantages are that the JP3 is better fixed via a THT connector, the GND is already present i the pin 10 and the 3V3 can be routed from a better location:

Best regards,
Marcelo

I'm little bit pissed of because I have been reversing this board since summer and now I've discovered this repo. :D But never mind, here's a doc I've been able to produce:

https://docs.google.com/spreadsheets/d/1L9uFN9jnsFd8CrgWXQyUStC2SsfoM5j2a6bWrxqi1Ko/edit#gid=0

Just this week I started to grind off and document PCB layers of this board. I have first layer off, slowly reaching the second one. Are there any more layers which need to be discovered or can I throw the board to trash?

It seems like gen_lpf.py is not aware of the chosen package. So when running make there is an error about L17 not beeing available on the CSFBGA285 package.

What should be done to make it work?

Hi,

This is a great work, guys! But it'll be even greater if the original LED matrix driving logic in FPGA can be reverse-engineered and shared here! I'm currently working on a project to develop a FPGA LED matrix display driver using Xilinx LX9. Would love to have some reference codes handy.

Thanks!

I ordered a 5A-75B but seller send me a E80 receiving card...

https://www.colorlightinside.com/Products/i%20Receiving-series/34_133.html

Do you know if they are the same pinout ??
All the JTAG pinout seems to be same : J27, J31, J32, J30
Power is still J33, J34

Only different is the buffer chips are MW245B ...

Thanks

According to my tests, the pinout has them both swapped around, B on the HUB75 connectors is F2 and D is E2.

I build platform.bit and program him in fpga. Fpga not response on ping 192.168.1.50.

On this photo ping work.
@enjoy-digital

This repo seems to have grown support for multiple parts now;

• RV901T LED "Receiver Card"
• Colorlight 5A-75B

It would be good to update the README to reflect that (and maybe the directory structure too?).

It seems like there are other potential boards in this series that might be added in the future too? See #20

How do I send data/stream to this controller from my c# program?

Folks,

On 7.0 board, PROGRAMN appears to available on the Eastern end of R106 (the end closest to the recycle symbol). Leastways, I can pull it and have it reboot correctly (including into secondary images, so it's not just shorting the rail).

...in case you want to add it in.

DAVE

Howdy.

After an investigation, I have concluded that there is no user accessible pin connected to the flash SCLK. Instead, you can use the USRMCLK primitive. This worked for me:

spiclk (
    .USRMCLKI(clock_i),
    .USRMCLKTS(0)
);

On the 5A-75E V6.0 board J16 has an inconsistent FPGA assignment.
HUB75 pins 1 and 6 are both assigned to FPGA Pin F14.
This is likely a typo.

I connected Sipeed RV Debugger (based on FT2232D) probe to 5A-75B v8.0 board using pinout from this diagram (and ground).
Using openFpgaLoader:

# openFPGALoader --verbose-level 2 -c ft2232 --detect
Jtag frequency : requested 6.00MHz   -> real 6.00MHz 
Raw IDCODE:- 0 -> 0xfc000003
JTAG init failed with: Unknown device with IDCODE: 0xfc000003 (manufacturer: 0x001 (), part: 0x60 vers: 0xf

Using openOCD:

# openocd -f ft2232d.cfg  -f chubby.cfg 
Open On-Chip Debugger 0.11.0+dev-00693-g0a36acbf6 (2022-05-27-10:14)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
adapter speed: 100 kHz

Info : clock speed 100 kHz
Info : JTAG tap: lfe5u25.tap tap/device found: 0xfc000003 (mfg: 0x001 (AMD), part: 0xc000, ver: 0xf)
Warn : JTAG tap: lfe5u25.tap       UNEXPECTED: 0xfc000003 (mfg: 0x001 (AMD), part: 0xc000, ver: 0xf)
Error: JTAG tap: lfe5u25.tap  expected 1 of 1: 0x41111043 (mfg: 0x021 (Lattice Semi.), part: 0x1111, ver: 0x4)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
Warn : gdb services need one or more targets defined
shutdown command invoked

ft2232d.cfg:

adapter driver ftdi
ftdi vid_pid 0x0403 0x6010
ftdi layout_init 0x0008 0x2b

transport select jtag
adapter speed 100

chubby.cfg:

jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8

init
scan_chain
shutdown

This probe has been successfully used with other jtag/swd targets.
Except for the JTAG board is fully working, connects with LEDset and Ledupgrade software via Ethernet.

Has the network protocol for sending video to the Colorlight cards been reversed?

I'd like to use them to drive some LED panels with a RPi4.

I'm aware of this: https://github.com/FalconChristmas/fpp/blob/master/src/channeloutput/ColorLight-5a-75.cpp as a partial reversed protocol. I'm wondering if there is a more complete one.

They mention "(info based on mplayer ColorLight 5a-75 video output patch)" and I assumed I would be able to find more thorough documentation there but haven't been able to find the patch they're referring to.

I found a few alternative implementations such as this project: https://github.com/NiklasFauth/colorlight-led-cube but don't really have the Verilog background to edit them for my needs. :(

I think some research should be done on this board since it is RK3188 and receiving card all in one. It easily outputs all the content directly on to the screen that you draw in the android app.

It’s using Altera Cyclone IV EP4CE6F17C8N

I have added the support of these boards in IceStudio
IceStudio is a visual editor for open FPGA boards.
You can get more information in my github
In my Github I explain that you can use three different JTAG programmers compatibles with the boards and IceStudio:

• FT2232H
• FT232H
• USB Blaster
  The use of other JTAG programmers are not recommendable; for example the STM32 with DirtyJTAG, it is too slow (more than 50 sg)

I’ve just acquired a v8.0 5A-75E board. It’s not mentioned here, and the JTAG (?) connectors are a square now, not a row. Will try to analyse over the next few days.

I need help with Colorlight 5A-75E v 6.1 receiver cards. After installing firmware version 5A 11.04.fw via LED upgrade software into Colorlight 5A-75E v 6.1 receiving cards. Receiving cards start up but the LED is solid green and receiving cards are not displayed in the ledvision and ledupgrade software. How would you advise to return the old firmware and functionality to the receiving cards. Thank you

Hi,

What is the part number for the USB to JTAG adapter used here ?

Thanks
Kind regards
Kiran Kanchi

To use inputs for ColorLight 5A-75B/E, I was thinking what about rewiring a buffer IC's pin 1 (the direction pin) to disconnect it from Vdd and instead connect it to ground? It would require physically breaking pin 1's connection to the board cause the pin sits on Vdd rail. Then could carefully solder a wire to it and an exposed ground.

Would also need to power the entire board using 3.3V instead of 5.0V, since the FPGA pins are surely not 5V-tolerant. (The only things the positive rail powers are the buck converters, but according the data sheet the 3.3V buck converters can still work with 3.3V input...the output just can't be higher than the input.)

I have been trying in vain to get this project working. It seems there is always an issue with the litex dependencies.

For instance, this is one of the problems I am having:
ImportError: No module named 'liteeth.phy.s6rgmii'

Can anybody give me a hint to how to install all the litex and migen components for this project?

Thanks

I've received a new batch of 5A-75E cards. Unfortunately this is a version 8.2 card. This card has the same FPGA and memory as the previous card, however I suspect that the pinout is different: I cannot connect with etherbone with this card. Does anybody else had some more success with a V8.2 card?

On the other hand: How to do pin mapping for PHY?

Hello,
Do you have the EEPROM dump from this board and likely to share? It seems I bricked the one on my board.

Thanks,
Dnstje.

Hi, saw this 16 port card and was wondering if anyone knew what fpga/memory was on it, its pinout, etc. It has a microcontroller and fpga according to the PDF, and apparently firmware updates for both can be done over the network with something called NovaLCT.

Firmware and specs are available if you scroll down here.

Direct links - specs, firrmware zip.
I also saw older specs on another site.

Note that all firmwares seems to be compressed in an unknown way, or (more likely) encrypted. All I get out of binwalk is that the entropy is very high. There don't seem to be any null sequences in the files, and the sizes are evenly divisible by 2k.

The spec sheet seems to indicate these may be driven directly by software, rather than a dedicated sender card, so I wonder if it contains more memory than the other receiver cards.

One other interesting thing about this card is that the level shifters seem to be on the back, which could make removing them easier if bidirectional IO is desired.

Heading is:
Colorlight 5A-75B V1.0 Hardware

For RV901T, the I/O direction of some of the 74HC245 buffers can be set by the FPGA on pin F13 (U600-U607, see Section Buffer. But the VDD on U600-U607 is at 5 V and like also mentioned in #37 for the 5a-75B, the 74HC245 buffers drive the FPGA inputs at 5 V when configured as an input buffer (the 74HC245 is directly connected to the FPGA pins). According to Xilinx, the Spartan-6 is not 5 V tolerant, meaning that it would damage or destroy the FPGA if the buffers are configured as inputs.

Am I missing something or is the board really designed that way?

Shouldn't this be mentioned in the Hardware description?

At least, the DIR input of the buffers is pulled to GND by R608, so during configuration of the FPGA, the buffers are configured as outputs and likely stay like this if the new design does not configure F13.

Hi!

I saw this post on Twitter showing a HUB75 FPGA board with an ECP5 instead of a Spartan-6. I plan on reverse engineering it, and I think many other people would be interested in joining the venture.

Should we publish our RE investigations here or create another repo instead?

Wondered how the outputs can be turned into inputs. On the 5a-75B when changing TC74VHC245 direction pin it would probably feed 5V into FPGA? so maybe powering from 3.3V instead of 5V would solve that? Does the board work when powered from 3.3 or can the vcc to TC74VHC245 be changed to 3.3V

Thinking about interfacing it with 5V CPU bus like the C64 cartridge connector.

BTW there is also 5a-75e https://www.aliexpress.com/item/32836510389.html having same Lattice FPGA and twice the connectors, also some listings like this one https://www.aliexpress.com/item/33010384708.html say "Wide working voltage range with DC3.3~6V." so maybe the output of that one is not 5V?

The FPGA Pin remains unknown. Too sad, I would have loved to use this port for my LED cube.
Does anyone know what this Pin connects to, or do I need to sacrifice a board to find out?

LG Niklas

Anyone tried upgrading the Colorlight 5A-75B RAM from 2 x 1M to higher capacity ??

Thanks

Hi!

I'm currently looking into buying some of these receive cards and I've seen, that there is a presumably newer Board called RV908. It looks like the RV901 with the HUB75 daughter board integrated.
Would it be possible to add support for this version too?

Regards!

Is it possible to add some more information about how to use OpenOCD?
Like configuration files and some basic command's what ever on how to verify connection and deply a design on the fpga.

I have a Colorlight 5A-75E V7.1 board, this is the board with 16 HUB75 connectors, and I am working on documenting the pinouts. It was going well and I used pin_scan to find the mapping for the HUB75, SDRAM, PHY, LED, BUTTON and flash pins.

I then realized that the pin_scan Makefile defaults to CABGA381 and the 5A-75E uses a CABGA256. I changed the Makefile and altered gen_lpf.py to use column 9 from the CSV mapping file. I cleaned, rebuilt and loaded the bit stream into the FPGA. It doesn't work! I don't see any UART output for the pins. Again, the CABGA381 compiled version works well.

I am perplexed as I wanted to provide an update to this project to support the 5A-75E but I don't know if what I have is reasonable. I have attached the document that I currently have for the 5A-75E.

Cheers,
Derek

hardware_V7.1.txt

Where can you get these boards from?

I was wondering if anyone already tried to stuck all these pieces of work together and managed to implement an eg. OPC sink to control HUB75 or WS2812 leds with this board.

If not, what work would be necessary?

• Niklas