pitronicteam / foc_esc-hardware Goto Github PK

Test points help with system integration and verification.

Please add test points for:

• the phase current measurement
• the input voltage
• the gate drive (pwm)

R2, R5 etc. are not necessary, they are built into the bridge driver in the SOC
See: datasheet

• Figure 12-2 Typical Gate Driver Connections
• Figure 12-3 High-Side Switching Transients and Optional Circuitry

Pwm/single wire input is not convenient for testing or as a single interface. Please add support for additional serial communication interfaces. I suggest simply breaking out to test pads or otherwise pins PE0~PE3.

This will allow spi, uart, i2c and can according to Table 18-1 PAC5523 Peripheral Pin MUX:

https://active-semi.com/wp-content/uploads/PAC5523_Datasheet.pdf

In order to facilitate the participation of others who do not have Altium Designer, please add the schematic diagram in a rendered format.

https://active-semi.com/wp-content/uploads/PAC5523_Datasheet.pdf

Datasheet Figure 10-2 shows resistor between vcc_in and VHM. It is not present in your design:

https://github.com/AirFleetTeam/FOC_ESC-hardware/blob/master/files/FOC_ESC%20Schematic%20V1.0.pdf

Why should we make that change? Please describe.
TVS diode will clamp input voltage and prevent spikes from frying the attached peripherals.