Comments (2)
Hello, sorry I have seen this message only now.
Yes the prediction is "not taken" and when the branch is taken, the controller sets pc_set_o that flushes the IF stage and the instruction in the ID is not executed.
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Thanks.
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Related Issues (20)
- Issue #722 correction introduced latches in combinatorial process HOT 1
- What is "MPEC" that is mentioned in the documentation? HOT 2
- Why aren't post-increment loads with RD==RS1 treated as illegal? HOT 6
- Help needed: Integration of cvFPU with cv32e40p and adding a custom instruction HOT 5
- HW Loop Constraints question HOT 5
- Error in Analysis and Synthesis in Quartus HOT 21
- Missing files HOT 3
- Seeking Information on RTL Access HOT 8
- Incorporating FPU HOT 2
- Suggested update to the FPGA Synthesis sub-section of the User Manual HOT 1
- cv32e40p_obi_interface: When TRANS_STABLE=0, unstable transaction can still pass through to obi interface. HOT 4
- Branch predictor in cv32e40p core will take more time. HOT 8
- cv32e40p_prefetch_buffer: Is it ok to assert hwlp_jump_i when there are no outstanding instr_ requests (ie cnt_q == 0)? HOT 4
- How can I build this core? HOT 2
- cv32e40p implementation on Arty a7 100T FPGA HOT 2
- Missing case default HOT 1
- Impossible to cover case default HOT 1
- FPU power consumption HOT 1
- Clarification on cv.clipr signedness HOT 2
- HWLoop count not updated when last instruction is a CSR access with pipeline flush HOT 1
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