Seeking Information on RTL Access about cv32e40p HOT 8 CLOSED

I have used ModelSim and Xmverilog.

from cv32e40p.

Hi @arunvthampi, thanks for your interest in the OpenHW Group. We maintain the CORE-V family of RISC-V cores, and this repository hosts the RTL for the one of those cores, the CV32E40P. I strongly recommend you start with the User Manual.

By the way, are you working with @vidushiy25 and @Amal-k-Ayyan? In recent days we have received a number of issues and emails from people asking how to get started with this core (see Issues #943 and #945). If you are members of the same team or class, perhaps we can organize a "how to get started" seminar for you.

from cv32e40p.

Hi @MikeOpenHWGroup , we're not on the same team or class, but thank you! I have understood my way around the cv32e40p files with the help of the User Manual and experimental testbenches. The Manual has been useful, thanks but I am still facing problems with Quartus. Simulation works perfectly fine but Analysis and Synthesis in Quartus is giving erros.

from cv32e40p.

Interesting. As far as I know, none of the OpenHW Group members use Quartus. I will check on this...

Which simulator are you using?

from cv32e40p.

Yes, I am working with Amal K Ayyan. Is it possible to get the seminar

from cv32e40p.

Is it possible to get the seminar

Reach out to me at [email protected].

from cv32e40p.

Hi @MikeOpenHWGroup , we're not on the same team or class, but thank you! I have understood my way around the cv32e40p files with the help of the User Manual and experimental testbenches. The Manual has been useful, thanks but I am still facing problems with Quartus. Simulation works perfectly fine but Analysis and Synthesis in Quartus is giving erros.

Just made a try using quartus prime pro 22.1.0 and everything works fine.

from cv32e40p.

Hi @arunvthampi, have your questions been answered? If so, please close this issue.

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