Debug halt causes illegal instructions about cv32e40p HOT 5 CLOSED

An update - we seem to get around the problem by reading the value of DBG_NPC and writing it back to cause a pipeline flush, as in: https://github.com/embecosm/ri5cy/blob/verilator-model/verilator-model/testbench.cpp#L279

Is this a bug somewhere, or is it always required to read/write DBG_NPC before resuming/single-stepping?

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We also noticed that the problem isn't just limited to the debug unit - whilst executing some programs that stall the pipeline with a load, the contents of the prefetch fifo become corrupted.

It turns out that we observe these issues only when INSTR_RDATA_WIDTH is 32, and the prefetch_buffer (prefetch_32) is used. When INSTR_RDATA_WIDTH is 128 and the prefetch_L0_buffer (prefetch_128) is used, we can use the debug unit without flushing the pipeline by writing to DEBUG_NPC, and the programs that stalled the pipeline don't seem to result in the contents of the fifo getting corrupted.

Is it possible that there's an issue with prefetch_buffer? I notice that the last commit to it (cc82192) was intended to address issues like the one we are seeing - could we be hitting an edge case that somehow got through?

Or maybe there's something else that needs to be done that we're not doing when using the prefetch_buffer?

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Hello,

thanks for reporting it!

I will try to replicate it, can you tell us more details to replicate such pipeline issue?

Maybe some waveforms or the piece of code with relative stalls would be also helpful for us.
Let us start with the example without debug :)

Thanks a lot,
Davide

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I've just tried changing INSTR_RDATA_WIDTH back to 32 in the most recent revision (was using 128 to workaround the issue as mentioned above), and I can no longer replicate the issue - I guess some of the changes recently that made fixes to the prefetcher have maybe resolved it?

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Hello,

I have actually fixed the prefetcher buffer in these 2 commits:

7078fa8

and here

5fb7e42

I hope this also solved your issue :)

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