merledu / caravan Goto Github PK

For a standard single read/write cycle we need atleast a host (master) and device (slave) interface.

Each protocol will have its own concrete request/response bundle. So the classes defined here: https://github.com/merledu/caravan/blob/main/src/main/scala/caravan/bus/wishbone/WishboneBus.scala#L43 should be more specific to Wishbone. The name could be WBRequest instead of just Request.

Need to update the docs with 2 new functionalities in Caravan Docs.

• A section for Wishbone and TL-UL in the User's Guide indicating that these two bus protcols can be used by user in their design in this way.
• Addition of Adapters in the User Guide, that the user can also use complete Adapters for Tilelink and Wishbone instead of creating one manually with host and device

The user might not need to pass the memory dump file. It should be kept optional and should not be a requirement.

Need to verify the Tilelink Uncached Lightweight implementation in Caravan.

• Refer to the Tilelink Specs for TL-UL Protocol.
• Match the Specs to the TL-UL Implementation in Caravan.

An example folder can be added containing an example of point-to-point as well as 1:N bus topology that the user can create with Wishbone interfaces. Also provide information regarding how can they integrate this design into their own use cases.

A wishbone master interface is required for the minimal communication over the bus.

Need to verify Wishbone implementation in Caravan.

• Refer to Wishbone Specs.
• Match the Specs with the Wishbone Implementation in Caravan.

Tilelink gives valid signal high at every 2 clock cycles in response although the data is not correctly fetched while wishbone gives valid response high at correct time.