Comments (3)
class SpiHarness(implicit val config: TilelinkConfig, spiConfig:Config) extends Module {
val io = IO(new Bundle {
// bus interconnect interfaces
val req = Flipped(Decoupled(new TLRequest()))
val rsp = Decoupled(new TLResponse())
// master spi interfaces
val cs_n = Output(Bool())
val sclk = Output(Bool())
val mosi = Output(Bool())
val miso = Input(Bool())
})
val hostAdapter = Module(new TilelinkHost())
val deviceAdapter = Module(new TilelinkDevice())
val spi = Module(new Spi(new TLRequest(), new TLResponse()))
hostAdapter.io.reqIn <> io.req
io.rsp <> hostAdapter.io.rspOut
hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
spi.io.req <> deviceAdapter.io.reqOut
spi.io.rsp <> deviceAdapter.io.rspIn
io.cs_n := spi.io.cs_n
io.sclk := spi.io.sclk
io.mosi := spi.io.mosi
spi.io.miso := io.miso
}
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@Talha-Ahmed-1 Looking into it
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Can you provide the test case or the Harness you are using it with?
So, I can look into the problem causing the issue !!
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Related Issues (11)
- Wishbone Master interface is required HOT 1
- TL-UL Verification HOT 7
- Wishbone Verification
- Update User's Guide in Docs
- Wishbone Slave interface is required HOT 1
- Update the docs to reflect latest changes in the API HOT 1
- Make the testbenches of harness self-checking HOT 1
- Add an examples folder for API showcase
- Rename the Request/Response bundle HOT 1
- Make the -DmemWrite argument optional HOT 1
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