Hi,
I am trying to design a BMS board based on what Texas Instruments have published as the evaluation board and what you have designed as a practical example. The problem I have is with the part you called "Source follower for decreased voltage drop in internal LDO (100V N-MOS)". The FET is getting really hot! The VC5X port of the chip is pulling the Gate up to 9 volts but the Source is somehow already at 8 volts so the Vgs is more or less 1 V and I think this is the problem because it increases the Rdson which can result in more power dissipation in the FET. I've seen some designs with a 200 Ohm resistor connected between the Source and the capacitor which may solve my issue as well but I think this may result in more power dissipation in the bq76940 itself which can't be good but that's a solution none the less.
Also, I only have a STM32F103VET6 and some 10K pull-up resistors on the board and the internal LDO is supplying 3.1 V with 37 mA right now. Is this too much?!
I've attached the schematic file to my board if you could kindly check it.

Thank you.

EmbededSystem.zip

Very nice project. I am designing a custom BMS based (bq76930 10s) on your work. Thank you very much for such work.

I have a couple of questions:

• Is MCU STM32F072CB or STM32F072C8 series?

• Is STM32F072RBT6 (64 pin version) compatible with your bms firmware?

• Is CRC mandatory to commucate with MCU? CRC or without CRC which one is compatible with your bms firmware?

• Is LDO voltage relevant? Which is prefered?2.5 or 3.3?

• Is "rev2" branch hw design tested?

Thanks

What are the specifications for this board? specially compared to http://electrodacus.com/SBMS100/manual/SBMSmanual.pdf

The CAN_STB pin is not wired because of naming mismatch, so the CAN transceiver cannot be switched on. Workaround: Hard-wire it to GND.

The cell voltage measurements of cell 5 and 6 (also cell 10 and 11 with bq76940) are influenced by the balancing current of the adjacent cell in the other cell group.
The voltage deviation depends on the resistance between BMS and cell, in my case it was about 15-20mV. With this error the BMS can't achieve an accurate balancing.
This happens because the clocks of the 2 or 3 cell groups are not synchronized.

From "bq769x0 Family Top 10 Design Considerations" (SLUA749A) chapter 4 p. 9:

The timelines of the cell groups in the bq76930 and bq76940 are independent, so one group may be balancing while the next group is measuring. At the cell boundary between groups, the adjacent cell may measure a voltage from the balance current in any common path. Keeping the common path resistance low, using wide traces or returning the current as close to the cell as possible will reduce this effect (see Figure 8).

Working solution/workaround: Remove the connections between VC5/VC5B and VC10/VC10B on the board and connect them to the respective cell with separate wires. Therefore the cells connector should be changed to a 20 pin model.
With 10s version it is possible to use one of the spare pins C11-C15 (see attached photos of my hacked board):

EDIT: I misunderstood some basics. I am all good with the 10 cells possibility :)

Hi,

I am currently planning to build a 24V Batterypack with 16 Headway LifePO4 40152S 15Ah Cells. Which I would need 8 in Serie for 24V and would like to have 2x8Series in parallel for a 16Cell total. The goal is to power my room with 220Wp Solarpanel on 24Volt.

I like your project and I hope and some point you can ship the solarcharger and BMS to interested people.

My feature request would be to support more than 10cells, if that not the case yet, so that me and other can use the BMS in future.

Keep up the incredible work!