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System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Why you choose range random (10000 loop) ?
I think if only 10000 loops are selected, the jump rate for each case will not be equal and can't cover all the points.
Hi gupta409,
I run your code with vcs simulator but get scoreboard issue about LOAD and MOVE command.
UVM_ERROR processor_scoreboard.sv(264) @ 11030000: uvm_test_top.env.sb [LOAD_FAIL] Actual Calculation=16384 Expected Calculation= 0
UVM_ERROR processor_scoreboard.sv(311) @ 46630000: uvm_test_top.env.sb [MOVE_FAIL] Actual Calculation= 154 Expected Calculation= 0
Please support me how to passed your testbench without any UVM_ERROR.
Please refer to run log file attached.
Regards,
Luan.
Hello, I am currently learning the relevant knowledge of UVM, and hope to get more familiar with VUVM through this project of yours. I saw that the makefile you uploaded was compiled through VCS. I hope to be able to compile through questa sim. In this case, what kind of makefile modification is required? Looking forward to your reply!
It would be nice to have a ready to run version of the project in EDA Playground. This would require loading the code and setting up the project in EDA Playground. Finally making it ready compile and run.
Currently the project is in it's extremely vanilla form. There is a need for details to be listed in the Readme.md.
Most of the details can be found in the Documentation directory.
Also need documentation on build and install of project.
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