firesim / icenet Goto Github PK

Hi icenet author,

I am interested in the cache coherence between the IceNIC DMA module and the dcache in the rocket-chip cores.

As far as I know, the IceNIC DMA module directly reads from and writes to the memory. However, I don't find any cache flush codes in the icenet driver. Therefore, IceNIC may read stale data from memory. But there is no such errors during firesim emulation.

So my question is how IceNIC ensure cache coherence so that DMA module works correctly with dcache in the rocket-chip cores while there is no cache flush instructions.

Best,
Liu