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dbgbus's Introduction

Debug Bus Interface(s)

This depository consists of a series of debugging bus interfaces.

Each interface connects an external debug port, whether UART, SPI, JTAG, or RPI Parallel port, to the master port of a wishbone bus. Hence, the debug interface allows you access to any device located on the wishbone bus--both to read from and write to that bus.

It is my intention to use the various components of each of the busses as teaching tools on the ZipCPU blog. Indeed, if you look at the topics page of the blog, you'll see that the series is now complete.

License

All of the files in this repository are licensed by either GPLv3 or the LGPL. For example, the simple HEXBUS interface is licensed under the LGPL, whereas the other interfaces are (or will be) licensed under GPL. Should the license provided be insufficient for your needs, please feel free to contact me for the terms necessary for a more appropriate license.

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dbgbus's Issues

make error at the top

I get the following error when running make at the top level of dbgbus ,and

verilator -Wall --MMD -trace -y ../../hexbus/rtl --Mdir obj_dir -cc testbus.v
make --no-print-directory -C obj_dir/ -f Vtestbus.mk
/usr/bin/perl /home/zone/Downloads/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtestbus.cpp Vtestbus___024root__DepSet_h3d88c857__0.cpp Vtestbus___024root__DepSet_hbe927a50__0.cpp Vtestbus__Trace__0.cpp Vtestbus__ConstPool_0.cpp Vtestbus___024root__Slow.cpp Vtestbus___024root__DepSet_h3d88c857__0__Slow.cpp Vtestbus___024root__DepSet_hbe927a50__0__Slow.cpp Vtestbus__Syms.cpp Vtestbus__Trace__0__Slow.cpp > Vtestbus__ALL.cpp
ccache g++ -I. -MMD -I/home/zone/Downloads/verilator/include -I/home/zone/Downloads/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o Vtestbus__ALL.o Vtestbus__ALL.cpp
echo "" > Vtestbus__ALL.verilator_deplist.tmp
Archive ar -rcs Vtestbus__ALL.a Vtestbus__ALL.o
rm Vtestbus__ALL.verilator_deplist.tmp
verilator -Wall --MMD -trace -y ../../hexbus/rtl --Mdir obj_dir -cc quikbus.v
make --no-print-directory -C obj_dir/ -f Vquikbus.mk
/usr/bin/perl /home/zone/Downloads/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vquikbus.cpp Vquikbus___024root__DepSet_h449c97b8__0.cpp Vquikbus___024root__DepSet_h451c77ba__0.cpp Vquikbus__Trace__0.cpp Vquikbus__ConstPool_0.cpp Vquikbus___024root__Slow.cpp Vquikbus___024root__DepSet_h449c97b8__0__Slow.cpp Vquikbus___024root__DepSet_h451c77ba__0__Slow.cpp Vquikbus__Syms.cpp Vquikbus__Trace__0__Slow.cpp > Vquikbus__ALL.cpp
ccache g++ -I. -MMD -I/home/zone/Downloads/verilator/include -I/home/zone/Downloads/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o Vquikbus__ALL.o Vquikbus__ALL.cpp
echo "" > Vquikbus__ALL.verilator_deplist.tmp
Archive ar -rcs Vquikbus__ALL.a Vquikbus__ALL.o
rm Vquikbus__ALL.verilator_deplist.tmp
Building dependency file
g++ -Og -g -Wall -I/home/zone/Downloads/verilator/include -I../rtl/obj_dir -I../../sw/host -I../../sw -c testbus_tb.cpp -o obj-pc/testbus_tb.o
In file included from testbus_tb.cpp:50:
testb.h: In instantiation of ‘TESTB::TESTB() [with VA = Vtestbus]’:
testbus_tb.cpp:63:52: required from here
testb.h:57:12: warning: ‘new’ of type ‘Vtestbus’ with extended alignment 64 [-Waligned-new=]
57 | m_core = new VA;
| ^~~~~~
testb.h:57:12: note: uses ‘void* operator new(std::size_t)’, which does not have an alignment parameter
testb.h:57:12: note: use ‘-faligned-new’ to enable C++17 over-aligned new support
g++ -Og -g -Wall -I/home/zone/Downloads/verilator/include -I../rtl/obj_dir -I../../sw/host -I../../sw -c uartsim.cpp -o obj-pc/uartsim.o
g++ -Og -g -Wall -I/home/zone/Downloads/verilator/include -I../rtl/obj_dir -I../../sw/host -I../../sw -c /home/zone/Downloads/verilator/include/verilated.cpp -o obj-pc/verilated.o
g++ -Og -g -Wall -I/home/zone/Downloads/verilator/include -I../rtl/obj_dir -I../../sw/host -I../../sw -c /home/zone/Downloads/verilator/include/verilated_vcd_c.cpp -o obj-pc/verilated_vcd_c.o
g++ -Og -g -Wall -I/home/zone/Downloads/verilator/include -I../rtl/obj_dir -I../../sw/host -I../../sw obj-pc/testbus_tb.o obj-pc/uartsim.o obj-pc/verilated.o obj-pc/verilated_vcd_c.o ../rtl/obj_dir/Vtestbus__ALL.a -o testbus_tb
obj-pc/verilated.o: In function VerilatedContext::threadPoolp()': /home/zone/Downloads/verilator/include/verilated.cpp:2504: undefined reference to VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)'
obj-pc/verilated_vcd_c.o: In function std::thread::thread<void (VerilatedTrace<VerilatedVcd, VerilatedVcdBuffer>::*)(), VerilatedTrace<VerilatedVcd, VerilatedVcdBuffer>*, void>(void (VerilatedTrace<VerilatedVcd, VerilatedVcdBuffer>::*&&)(), VerilatedTrace<VerilatedVcd, VerilatedVcdBuffer>*&&)': /usr/include/c++/9/thread:130: undefined reference to pthread_create'
collect2: error: ld returned 1 exit status
Makefile:105: recipe for target 'testbus_tb' failed
make[1]: *** [testbus_tb] Error 1
Makefile:83: recipe for target 'sim' failed
make: *** [sim] Error 2

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