Comments (4)
Yes, the problem was the 1'b_
. This should be a syntax error, but it was easier to fix it so that this is the same as 1'b_0
, which I have now done in commit 4b8200e.
Reduced test case:
module demo(output [63:0] y);
assign y = 1'b_;
endmodule
Apparently there is a similar bug in Icarus Verilog:
$ iverilog test.v
ivl: verinum.cc:364: verinum::V verinum::get(unsigned int) const: Assertion `idx < nbits_' failed.
sh: line 1: 2885 Done /usr/local/lib/ivl/ivlpp -L -F"/tmp/ivrlg25884e2fb" -f"/tmp/ivrlg5884e2fb" -p"/tmp/ivrli5884e2fb"
2886 Aborted | /usr/local/lib/ivl/ivl -C"/tmp/ivrlh5884e2fb" -C"/usr/local/lib/ivl/vvp.conf" -- -
Do you want to report that or should I?
Thanks for the bug report. Please keep fuzzing..
from yosys.
You should report it, I'm not familiar with icarus verilog.
from yosys.
Hi, @jeremysalwen , do you have any plan to open source your AFL dictionary for verilog?
from yosys.
@hailinzeng Yes, certainly. I just took the list of keywords from here: https://www.csee.umbc.edu/portal/help/VHDL/verilog/reserved.html and combined it with a list of all string constants from the yosys source code that began with backslash. http://pastebin.com/zzLDvLak
from yosys.
Related Issues (20)
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
- Inout can't be read with constant value HOT 3
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
- Unexpected Result from `synth_gowin` Pass HOT 4
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells) HOT 3
- Build error: `make: *** [Makefile:810: abc/abc] Error 2` HOT 4
- Documentation is unreadable if the system theme is dark HOT 5
- Wired-or (wor) wires generate $or / $reduce_or cells in output HOT 3
- Nothing of abc folder contents at git clone https://github.com/YosysHQ/yosys.git HOT 1
- Yosys seems to handle bit operations on empty strings inconsistently with the original design. HOT 4
- The negation operation on an empty string results in an exception. HOT 6
- Outputs differ before and after synthesis, but Yosys seems correct.
- read_verilog doesn't respect `signed` keyword HOT 2
- make error 'abc' is not configured as a git submodule. HOT 12
- CXXRTL: Information loss when outputs are aliased HOT 4
- Abnormal output
- create a pip install package wheel for Windows HOT 3
- Enhancing Syntax Checking for Port Declarations in Yosys HOT 2
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