Comments (2)
This doesn't seem like a valuable enhancement; to me it looks like a padding for your fuzzer's list of discoveries.
from yosys.
Per the README, the Yosys Verilog frontend intentionally allows trailing commas. I think many Yosys users already depend on this trailing comma behavior (enough that I've had to tolerate trailing commas in sv2v, too). As such, I don't think we can change the default behavior of read_verilog
to forbid trailing commas. Perhaps we could have a stricter parsing mode, but I'm not sure it would get much use. Some users also choose to pass their source through other tools such as verilator or iverilog for perform additional checks.
from yosys.
Related Issues (20)
- ASTNode::simplify has supralinear performance with deep nesting of expressions HOT 4
- "reg" values of typedeffed types HOT 1
- Problems with 3 bit add not passing eqy HOT 2
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- New `$check` flavors: `warning` and `error` HOT 3
- The wrong tag has been pushed for the 0.45 release HOT 2
- Get a proper command line parser HOT 1
- Github tag style HOT 5
- Synthesis with synth_xilinx crashes in TECHMAP pass HOT 2
- Inconsistency with how libyosys is imported in Python
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- Excessive recursion in simple program HOT 2
- Port names starting with '%' cause stack buffer overflow during error reporting HOT 2
- Importing init of memory is extremely slow HOT 1
- Synth_xilinx generates too many DSPs for simple multiplication HOT 2
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- Yosys Synthesis Fails with std::out_of_range Error in OPT_DEMORGAN Pass HOT 5
- Efficient handling of patterns emitted by sv2v HOT 6
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from yosys.