Comments (2)
I've now fixed the performance problem in git commit 9a34486.
Note that the code you posted is not valid synthesizable code! You create BITS+1
conflicting drivers for out
here. In cases like this with N conflicting drivers and latched logic (logic loops), the opt_mux pass had a complexity of O(N!). There was no performance problem in valid synthesizable code.
I think you intended to write something like the following instead:
/* Count leading zeroes by independent prefix comparison: works for non-power-of-two sizes: */
module count_leading_zeroes (in, out);
parameter BITS = 4; /* no problem */
/* set parameter BITS = 32 or some BIG_NUMBER and watch the optimizer spinning.... */
localparam OUT_BITS = $clog2(BITS) + 1;
input [BITS-1:0] in;
output reg [OUT_BITS-1:0] out;
integer i;
always @(*) begin
for (i=0; i<BITS; i=i+1) begin
if (in[BITS-1:BITS-1-i] == { { i { 1'b0 } }, 1'b1 }) begin
out = i;
end
end
if (in == 0) begin
out = { 1'b1 , { OUT_BITS - 1 { 1'b0 } } };
end
end
endmodule
This of course still models a latched logic block (logic loop), which is generally considered bad design style. So this version of your code only fixes the issue with the conflicting drivers.
from yosys.
That's indeed correct, thank you for the quick response! Is it possible to issue a warning in this case?
from yosys.
Related Issues (20)
- Extreme logic usage HOT 10
- Yosys Fails to Detect Syntax Violations According to Verilog Standards HOT 2
- Assertion Failure in genrtlil.cc When Handling Signedness Issue Description: HOT 1
- yosys fails with 'ERROR: init_share_dirname: unable to determine share/ directory!' on macos HOT 3
- Proof engine is going into wrong case in case statement HOT 3
- Parameters in other packages HOT 2
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
- Latch inferred for x signal HOT 4
- Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855
- Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors HOT 3
- Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports HOT 1
- Another out-of-memory problem with for loop
- synth_* passes should call `check -mapped`
- "ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design HOT 2
- Crash in yosys-abc
- Manual title page should have yosys version number
- Should -nomx8 be the default for the GateMate?
- opt: no "-purge" option but public names removed HOT 2
- Tests fails on Debian GNU/Linux on ppc64 HOT 6
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from yosys.