Comments (3)
(this reply is mostly me thinking out loud, in the hopes that if I get distracted I can come back to this and not have to redo too much work)
So, the quirky bit of the testcase here is that you have two wires: \outp__payload
and \outp__payload[0]
.
Inside the AIGER parser there is a little section of code which assumes that if it has encountered a wire before, it is the least significant bit of a wide wire, and renames it accordingly:
yosys/frontends/aiger/aigerparse.cc
Lines 923 to 925 in 77dff5a
except here it renames \outp__payload
to \outp__payload[0]
, which is a wire that already exists, and so Yosys asserts.
from yosys.
Fix ideas:
- detect this situation and rename wires and box ports appropriately (perhaps this issue exists in other parts of the codebase).
\outp__payload[0]
is an alias of\outp__payload
, so it's actually okay to use it here, I think. But how do I detect that?SigMap
?- insert a strategic
opt_clean -purge
, which resolves the aliasing and the problem goes away in both testcases.
from yosys.
Temporary workaround: Something like yosys -p "synth_ice40 -run :coarse; opt_clean -purge; synth_ice40 -run coarse:" input.v
from yosys.
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