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This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

Home Page: http://www.pynq.io/

License: BSD 3-Clause "New" or "Revised" License

Python 0.26% Tcl 6.26% Jupyter Notebook 92.81% C++ 0.44% Makefile 0.22%

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Replace DMA with AXI Master

Hi,

In this repo, we use DMA and the performance is poor. I guess it was because of the DMA & Data Width Converters.
However, if we want to replace the DMA with AXI Master, how can we use the kernel on IPython?

I tried allocating the buffers in PS memory, then passed their physical address to the kernel and set AP_CTRL=1. It returned a black image.

I think this approach helps user to go straight from kernel development to application development with Vitis, bypass the complicated system block design with Vivado.

Old:

Suggest:

error when running install command - cannot build wheels

Version: 3.0.1

I am trying to run the install command and am getting the following error.

ERROR: Failed building wheel for pynq-helloworld
Failed to build pynq-helloworld
ERROR: Could not build wheels for pynq-helloworld, which is required to install pyproject.toml-based projects

error when generating Vitis HLS in 2020.1: declaration of 'resize_accel' has a different language linkage

I get errors when making the Vitis HLS project, with the 2020.1 toolchain:
https://github.com/Xilinx/PYNQ-HelloWorld/blob/master/boards/ip/hls/resize/Makefile

ERROR: [HLS 207-2542] declaration of 'resize_accel' has a different language linkage: xf_resize_accel.cpp:68:53

The function is declared as C in the cpp file:
extern "C" {
void resize_accel ...

When I try to declare it the same in xf_config_params.h, I get different issues:

INFO: [HLS 214-178] Inlining function 'xf::cv::Mat<9, 2160, 3840, 1>::read(int)' into 'void resizeNNBilinear<9, 2160, 3840, 1, 1080, 1920, 1, 2>(xf::cv::Mat<9, 2160, 3840, 1>&, xf::cv::Mat<9, 1080, 1920, 1>&)' (../vitis_lib/vision/L1/include\imgproc/xf_resize_nn_bilinear.hpp:277:0)
INFO: [HLS 214-178] Inlining function 'xf::cv::Mat<9, 1080, 1920, 1>::write(int, ap_uint<24>)' into 'void resizeNNBilinear<9, 2160, 3840, 1, 1080, 1920, 1, 2>(xf::cv::Mat<9, 2160, 3840, 1>&, xf::cv::Mat<9, 1080, 1920, 1>&)' (../vitis_lib/vision/L1/include\imgproc/xf_resize_nn_bilinear.hpp:277:0)
ERROR: [HLS 214-194] in function 'resize_accel': Undefined function xf::cv::_ssdm_op_alloc (../vitis_lib/vision/L1/include\common/xf_structs.hpp:527:9)
ERROR: [HLS 214-134] in function 'axis2xfMat(axis_t*, xf::cv::Mat<9, 2160, 3840, 1>&, int, int)': Pointer to pointer is not supported
ERROR: [HLS 214-134] in function 'void resizeNNBilinear<9, 2160, 3840, 1, 1080, 1920, 1, 2>(xf::cv::Mat<9, 2160, 3840, 1>&, xf::cv::Mat<9, 1080, 1920, 1>&)': Pointer to pointer is not supported
ERROR: [HLS 214-134] in function 'xfMat2axis(xf::cv::Mat<9, 1080, 1920, 1>&, axis_t*, int, int)': Pointer to pointer is not supported
ERROR: [HLS 214-135] Syn check fail!
Pre-synthesis failed.
    while executing
"source D:/users/jancu/git_pynq/PYNQ-HelloWorld/boards/ip/hls/resize/resize/solution1/csynth.tcl"
    invoked from within
"hls::main D:/users/jancu/git_pynq/PYNQ-HelloWorld/boards/ip/hls/resize/resize/solution1/csynth.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"

I used this command to check out the GIT rep:
git clone --recursive https://github.com/Xilinx/PYNQ-HelloWorld.git

Then created the Vivado project using the resize.tcl script.
Then created the Vitis HCL project using the make script PYNQ-HelloWorld/blob/master/boards/ip/hls/resize/Makefile

Troughput

Hi, have you tested the throughput of both systems? I mean, time to resize the same image in PS and PL.
My results are around 48ms in PS and 30 in PL, what I think there is no much improvement, in comparison with other streaming tasks I have tested.

notebook change: detect available memory ports

This is related to #14 , where memory interfaces can vary from platform to platform. Has to adjust the notebook accordingly.

HLS Resize IP failed to compile

After trying to compile the resizer IP I got this Error:

ERROR: [HLS 200-70] Compilation errors found: In file included from xf_resize_accel.cpp:1:

I've googled a little and found similar problems, but none of them seem to really be helpful:

PYNQ-HelloWorld Issue 3
xfopencv Issue 37
Xilinx Forum

If I rather should post this issue to the https://github.com/Xilinx/Vitis_Libraries please Site please just tell me!
Thank you very much in advance! :)

I am running this on an Oracle VM with Ubuntu 16.04.6 and Vivado 2019.2

Full Message:

****** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:39:14 MST 2019
  **** IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source /tools/Xilinx_Vitis/Vivado/2019.2/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx_Vitis/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'noahs' on host 'noahs-VirtualBox' (Linux_x86_64 version 4.15.0-107-generic) on Thu Jul 09 15:35:22 CEST 2020
INFO: [HLS 200-10] On os Ubuntu 16.04.6 LTS
INFO: [HLS 200-10] In directory '/home/noahs/Documents/PYNQ-HelloWorld/boards/ip/hls/resize'
Sourcing Tcl script 'script.tcl'
INFO: [HLS 200-10] Opening project '/home/noahs/Documents/PYNQ-HelloWorld/boards/ip/hls/resize/resize'.
INFO: [HLS 200-10] Adding design file '../vitis_lib/vision/L2/examples/resize/xf_resize_config.h' to the project
INFO: [HLS 200-10] Adding design file '../vitis_lib/vision/L2/tests/resize/resize_DOWN_BILINEAR_NO_RGB/xf_config_params.h' to the project
INFO: [HLS 200-10] Adding design file 'xf_axis_config.h' to the project
INFO: [HLS 200-10] Adding design file 'xf_resize_accel.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'xf_resize_tb.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/noahs/Documents/PYNQ-HelloWorld/boards/ip/hls/resize/resize/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 2.7ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg484-2'
INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [HLS 200-10] Analyzing design file 'xf_resize_accel.cpp' ... 
ERROR: [HLS 200-70] Compilation errors found: In file included from xf_resize_accel.cpp:1:
In file included from xf_resize_accel.cpp:30:
In file included from ./xf_axis_config.h:37:
In file included from ../vitis_lib/vision/L1/include/common/xf_common.hpp:20:
../vitis_lib/vision/L1/include/common/xf_structs.hpp:436:10: error: too many template arguments for class template 'stream'
    hls::stream<DATATYPE, XFCVDEPTH> data;
         ^                ~~~~~~~~~~
/tools/Xilinx_Vitis/Vivado/2019.2/common/technology/autopilot/hls_stream.h:89:7: note: template is declared here
class stream
      ^
In file included from xf_resize_accel.cpp:1:
In file included from xf_resize_accel.cpp:30:
In file included from ./xf_axis_config.h:37:
In file included from ../vitis_lib/vision/L1/include/common/xf_common.hpp:20:
../vitis_lib/vision/L1/include/common/xf_structs.hpp:929:12: error: unknown type name 'constexpr'
    static constexpr int fvalue = 1 + (log2<N / 2>::fvalue);
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:929:22: error: expected member name or ';' after declaration specifiers
    static constexpr int fvalue = 1 + (log2<N / 2>::fvalue);
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:930:12: error: unknown type name 'constexpr'
    static constexpr int cvalue = (N > (1 << fvalue)) ? (fvalue + 1) : fvalue;
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:930:22: error: expected member name or ';' after declaration specifiers
    static constexpr int cvalue = (N > (1 << fvalue)) ? (fvalue + 1) : fvalue;
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:936:12: error: unknown type name 'constexpr'
    static constexpr int fvalue = 0;
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:936:22: error: expected member name or ';' after declaration specifiers
    static constexpr int fvalue = 0;
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:937:12: error: unknown type name 'constexpr'
    static constexpr int cvalue = 0;
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:937:22: error: expected member name or ';' after declaration specifiers
    static constexpr int cvalue = 0;
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:953:12: error: unknown type name 'constexpr'
    static constexpr int XF_BITS_PER_CLOCK = DataType<T, NPC>::pixelwidth * xfNPixelsPerCycle<NPC>::nppc;
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:953:22: error: expected member name or ';' after declaration specifiers
    static constexpr int XF_BITS_PER_CLOCK = DataType<T, NPC>::pixelwidth * xfNPixelsPerCycle<NPC>::nppc;
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:954:12: error: unknown type name 'constexpr'
    static constexpr int COLS_BOUND_PER_NPC = ((COLS + (xfNPixelsPerCycle<NPC>::nppc - 1)) >> xfNPixelsPerCycle<NPC>::datashift);
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:954:22: error: expected member name or ';' after declaration specifiers
    static constexpr int COLS_BOUND_PER_NPC = ((COLS + (xfNPixelsPerCycle<NPC>::nppc - 1)) >> xfNPixelsPerCycle<NPC>::datashift);
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:955:12: error: unknown type name 'constexpr'
    static constexpr int LOOPBOUND = ROWS * COLS_BOUND_PER_NPC;
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:955:22: error: expected member name or ';' after declaration specifiers
    static constexpr int LOOPBOUND = ROWS * COLS_BOUND_PER_NPC;
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:956:12: error: unknown type name 'constexpr'
    static constexpr int ADDRBOUND = ((ROWS * COLS * DataType<T, NPC>::pixelwidth) + (PTR_WIDTH - 1)) >>
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:956:22: error: expected member name or ';' after declaration specifiers
    static constexpr int ADDRBOUND = ((ROWS * COLS * DataType<T, NPC>::pixelwidth) + (PTR_WIDTH - 1)) >>
    ~~~~~~~~~~~~~~~~ ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:958:12: error: unknown type name 'constexpr'
    static constexpr int LAST_BLK_PXL_WIDTH =
           ^
../vitis_lib/vision/L1/include/common/xf_structs.hpp:958:22: error: expected member name or ';' after declaration specifiers
    static constexpr int LAST_BLK_PXL_WIDTH =
    ~~~~~~~~~~~~~~~~ ^
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
Failed during preprocessing.
    while executing
"source script.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [Common 17-206] Exiting vivado_hls at Thu Jul  9 15:35:33 2020...
Makefile:8: recipe for target 'hls' failed
make: *** [hls] Error 1

KV260 build folder

For tracking - we'll add a KV260 folder since PYNQ-Helloworld bitstreams exist for the Kria and are downloaded during Kria-PYNQ install.

Deprecation: Update the Xlnk calls to use allocate() ...

Okay for now, will be deprecated in >2.5 PYNQ releases

DMA地址的问题

resizer.write(0x10, old_height)
resizer.write(0x18, old_width)
resizer.write(0x20, new_height)
resizer.write(0x28, new_width)

def run_kernel():
dma.sendchannel.transfer(in_buffer)
dma.recvchannel.transfer(out_buffer)
resizer.write(0x00,0x81) # start
dma.sendchannel.wait()
dma.recvchannel.wait()
其中的 resizer.write(0x00,0x81) # start这条指令，(0x00,0x81)代表什么意思，从哪里可以得到它的地址呢？

若换成其他IP核怎么看它的地址？

pip3 install fails ModuleNotFound error

On PYNQ 2.5
REVISION : Release 2019_10_03 3f63450
Board: ZCU104

Brand new install on new SD supplied with board

Run from terminal: sudo pip3 install pynq-helloworld

returns:

edited to here:
Complete output from command python setup.py egg_info:
Traceback (most recent call last):
File "", line 1, in
File "/tmp/pip-build-5lwuk5f6/pynq-helloworld/setup.py", line 39, in
from pynq.utils import build_py
ModuleNotFoundError: No module named 'pynq.utils'

`xf_config_params.h` bound from the test instead of the actual example

I see that xf_config_params.h is included from a specific test instead of the actual source:

PYNQ-HelloWorld/boards/ip/hls/resize/script.tcl

Line 10 in b9ec77a

 add_files ../vitis_lib/vision/L2/tests/resize/resize_DOWN_BILINEAR_NO_RGB/xf_config_params.h 

These xf_config_params.h do not differ. Is there a logic behind including the file from the test?

installation from a direct connection

I have a question about the installation. The PYNQ board has a direct connection with a development machine, so the direct board-to-computer connection prevents the board from directly accessing the internet. How can I install and run an example ?

Thank you for your instructions very much.

AttributeError: 'Xlnk' object has no attribute 'bufmap' when installing on PYNQ-Z2

Pynq version: 2.5.2
Board: PYNQ-z2

an error raise up when run the last step "pynq get-notebooks pynq-helloworld -p ."

HLS Resize IP code does not compile

Resize IP HLS code fails on Vivado HLS 2018.3:

In file included from C:/Xilinx/Vivado/2018.3/include/hls_fpo.h:186:0,
from C:/Xilinx/Vivado/2018.3/include/hls_half.h:44,
from C:/Xilinx/Vivado/2018.3/include/etc/ap_private.h:90,
from C:/Xilinx/Vivado/2018.3/include/ap_common.h:641,
from C:/Xilinx/Vivado/2018.3/include/ap_int.h:54,
from ../../../../xf_resize_config.h:34,
from ../../../../xf_resize_accel.cpp:30:
C:/Xilinx/Vivado/2018.3/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
#define __GMP_LIBGMP_DLL 1

@e Simulation failed.
ERROR: [SIM 211-100] CSim failed with errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source hls_script.tcl"
invoked from within
"hls::main hls_script.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"

KV260 Image

Hi, I see that KV260 is also supported for this example, which image are you using for this?
As of now, I don't see any official version for same. Can you guys share your custom image?
Thank you.

Error when generate block design with resize.tcl

Hello! I'm using PYNQ-Z2, vivado 2020.1, and I want to generate a image resize IP with resize.tcl. But when I run it, an error occurred:

WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block!

WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block!

WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins resize_accel_0/src'

ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.

ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
while executing
"connect_bd_intf_net -intf_net axis_dwidth_converter_0_M_AXIS [get_bd_intf_pins axis_dwidth_converter_0/M_AXIS] [get_bd_intf_pins resize_accel_0/src]"
(procedure "create_root_design" line 71)
invoked from within
"create_root_design """
(file "D:/pynq/resize/resize.tcl" line 348)

Is the version of vivado is too new, as I just change the version limit. And I find a similar question here
Thanks.

Error Synthesising the resizer HLS

Dear,
We try to use your example for demo PYNQ on the Ultra96.
We use vitis 20.02 package on Ubuntu20.04, synthesing the resize HLS IP runs in code errors:

ERROR: [HLS 207-3332] type 'hls::stream<DATATYPE, 2>' (aka 'stream<ap_uint<24>, 2>') does not provide a subscript operator: xf_resize_accel.cpp:42:11
ERROR: [HLS 207-3332] type 'hls::stream<DATATYPE, 2>' (aka 'stream<ap_uint<24>, 2>') does not provide a subscript operator: xf_resize_accel.cpp:62:38
ERROR: [HLS 207-2538] declaration of 'resize_accel' has a different language linkage: xf_resize_accel.cpp:68:53

Before we dig deeper into the C++ code, is this related to HLS settings -as we use vitis_hls, not the 2019 vivado_hls ?
Or could the Vitis Vision-library have changed, we copied it from the repo.

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