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2dconv-fpga

A 2D convolution hardware implementation written in Verilog

3dcnn

3D convolutional neural network for video classification

8bit_datapath_aes

This is a 8-bit datapath hardware implementation of AES.

a-pytorch-tutorial-to-machine-translation

Attention Is All You Need | a PyTorch Tutorial to Machine Translation

a-pytorch-tutorial-to-super-resolution

Photo-Realistic Single Image Super-Resolution Using a Generative Adversarial Network | a PyTorch Tutorial to Super-Resolution

abu

阿布量化交易系统(股票，期权，期货，比特币，机器学习) 基于python的开源量化交易，量化投资架构

abu_ml

机器学习技术研究室——by阿布量化小组

accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-fpga

AES加密解密算法的Verilog实现

aeshw

andrewng-ml-python

Assignments of Andrew Ng machine learning course offered by Stanford on coursera In Python

assignments

autosa

AutoSA: Polyhedral-Based Systolic Array Compiler

awesome-domain-adaptation

A collection of AWESOME things about domian adaptation

awesome-ml-for-cybersecurity

:octocat: Machine Learning for Cyber Security

awesome-python

A curated list of awesome Python frameworks, libraries, software and resources

axi_uartlite_pynq

PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

baoforpostgresql

A prototype implementation of Bao for PostgreSQL

bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

blockchainacceleration

caffe

Ristretto: Caffe-based approximation of convolutional neural networks.

car

Content adaptive resampler for image downscaling

carpetfuzz

An NLP-based fuzzing assitance tool for generating valid option combinations.

cased-tensorflow

Simple Tensorflow implementation of "Curriculum Adaptive Sampling for Extreme Data Imbalance" with multi GPU using LUNA16 (MICCAI 2017) / LUNA16 Tutorial

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

chisel3

Chisel 3: A Modern Hardware Design Language

ck-request-asplos18-resnet-tvm-fpga

CK workflow, portable packages and other artifacts for the ReQuEST-ASPLOS'18 submission:

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

convolutional-neural-network

Implementation of CNN using Verilog