Comments (4)
A similar situation exists with computational outputs (output!) where this does no make any difference when the output is replaced by a wire (bound).
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Expression tracking is solved for the case of tracking another tracker, disallowing mixing ::= and :=
The case with outputs remains open (tracking an output; chaining outputs).
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Note that expression tracking changed terminology for 'expression binding' and now uses the operators <:
and <::
. The issue remains.
from silice.
Closing as this is now clarified and warnings are issued on such cases.
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Related Issues (20)
- Double check initializers for tables HOT 1
- Silice installs files back into the build directory HOT 3
- pipeline sync
- interleaving pipelined algorithms in host pipelines HOT 1
- Extracting bits from a bitfield results in a segmentation fault HOT 2
- Combining declaration and always assignment
- Many boards share a common set of features, yet each board has its own define HOT 2
- Empty FSM states could be optimized HOT 7
- Unused states that remain and cycles that could be avoided HOT 35
- Unexpected code execution. HOT 4
- Name shadowing
- Error initialising bram not brom
- A subroutine which is never called in a design can crash Silice. HOT 6
- Not setting a subroutines output parameter leads to a yosys error. HOT 2
- uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board HOT 1
- Can't compile Silice on Arch Linux HOT 14
- ULX3S sdram_memtest sample build fails. HOT 4
- **ASSERT FAILED** (if_deadend && !if_statless) || !if_deadend, file ..Algorithm.cpp, line 4078 HOT 3
- inouts cannot be bound using a bit-select syntax
- Documentation: possible typo in Silice/learn-silice/Documentation.md?
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