Comments (3)
Thanks for the report! This was a missing check in implementing the revised pipelines. This now correctly reports an error message and a changelog warning.
The error is due to changes in pipeline syntax (see CL0003 for details). To avoid this rewrite from
while (1) {
{ A } -> { B } -> { C }
if (...) { break; }
}
to
while (1) {
{ A -> B -> C }
if (...) { break; }
}
That is because the ->
operator, which divides the design into stages, now has a lower priority than the blocks.
There have been other changes to pipelines, in particular those in algorithm
blocks (the documentation is up to date), so you may want to adjust your design a bit to be closer to the prior behavior. For your use case I'd recommend changing from
algorithm main(output uint8 leds)
{
always_after { A }
while (1) {
{ S0 } -> { S1 } -> { S2 }
if (...) { break; }
}
}
to
unit main(output uint8 leds)
{
always {
{ S0 -> S1 -> S2 }
if (...) { __finish(); /*simulation only*/ }
A
}
}
This should be equivalent to the prior version.
Hope that helps!
Best regards -
from silice.
(Closing as solved for now, please let me know if the problem persists)
from silice.
Sorry. Thank you for the fix which solved the crash I experienced. However the resulting design didn't work as expected and I timed out understanding why and failed to update the github issue.
from silice.
Related Issues (20)
- Combining declaration and always assignment
- Many boards share a common set of features, yet each board has its own define HOT 2
- Empty FSM states could be optimized HOT 7
- Unused states that remain and cycles that could be avoided HOT 35
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- uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board HOT 1
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