Comments (6)
Hi Bernd, fix in both wip
and draft
, thanks for the report!
Best regards,
Sylvain
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Hello Sylvain,
thank you for the fix.
Regards, Bernd.
from silice.
Re-opening as my fix was actually incorrect. I pushed a correction in wip
and draft
, leaving open until further testing. Thanks to @rob-ng15 who detected the issue on PAWSv2!
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All working again.
from silice.
Hello Sylvain, hello Rob,
I tested the draft version with two of my (larger) designs and both were working correct.
Regards, Bernd.
from silice.
Thanks for the tests! I found another corner case, fixed in my local branch, keeping open until next push.
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Related Issues (20)
- Combining declaration and always assignment
- Many boards share a common set of features, yet each board has its own define HOT 2
- Empty FSM states could be optimized HOT 7
- Unused states that remain and cycles that could be avoided HOT 35
- Unexpected code execution. HOT 4
- Name shadowing
- Error initialising bram not brom
- Not setting a subroutines output parameter leads to a yosys error. HOT 2
- uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board HOT 1
- Can't compile Silice on Arch Linux HOT 14
- ULX3S sdram_memtest sample build fails. HOT 4
- **ASSERT FAILED** (if_deadend && !if_statless) || !if_deadend, file ..Algorithm.cpp, line 4078 HOT 3
- inouts cannot be bound using a bit-select syntax
- Documentation: possible typo in Silice/learn-silice/Documentation.md?
- Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram
- $$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */
- Enhancement of declaration of and usage of always assignments
- Unable to build just the ice-v CPU HOT 2
- silice-make.py fails on initial test after install on MacOS HOT 3
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