Comments (4)
Hi,
So until now, the idea was "If you want latches, you have to instanciate them through blackboxes"
But now it could be possible to integrate the feature in reworkDev branch, be before trying it, i would like to release the reworkDev branch into the master one, see if everything is fine, get some feedbacks, and later adding new feature of this order (latches).
Until that time, is the blaboxing way enough ?
Maybe those blackboxes could be integrated into devRework, and be instanciated via a wrapper. Then when the feature is nativly supported it would not need any changes in the user code base.
from spinalhdl.
Sure, latches are not so essential and blackboxing is OK.
Future/long term feature is totally fine.
from spinalhdl.
For the design I think a Latch(T)
would feel more natural (like Reg(T)
). With LatchWhen(...)
, etc.
So your example would be:
val d = Bool
val e = Bool
val l = Latch(Bool)
when (e) {
l := d
}
Or
val d = Bool
val e = Bool
val l = LatchWhen(d, e)
from spinalhdl.
Yes, Latch(T) seems more natural. That maybe just some makeup which would add addTag(noLatchCheck) under the hood
from spinalhdl.
Related Issues (20)
- how to drive inout IO ?for example i2c HOT 2
- XSim on Windows : getting it to work as expected through cmd or MSYS2(MINGW64) HOT 33
- 『Requirement And Idea』SpinalHDL generated verilog code parameterization and generate block simplification requirements. HOT 13
- Ability to specify path to make binary HOT 6
- Bad interaction between Bits.aliasAs and Data.as HOT 2
- How to understand the Simulated behavior in SpinalHDL? HOT 4
- spinal.lib.misc.pipeline refractoring
- SpinalConfig.generate does not work as expected When define two modules with implicit parameter in "generate" func HOT 7
- Axi4Stream: userWidth tied to dataWidth HOT 5
- Implicit parity signal in Bundle, freeze, and signalCache HOT 7
- Arbitrary data bundle type for Axi4Stream HOT 8
- Blackbox Verilog sources are not included in formal verification
- Vec as packed array in io HOT 9
- Issues with verilator 5 HOT 2
- Documentation / example usage for `Axi4ReadOnlyMasterAgent` and `Axi4WriteOnlyMasterAgent` HOT 5
- Signals in simulation pruned HOT 2
- Explain the lib:Apb3SpiXdrMasterCtrl.scala and SpiXdrMasterCtrl.scala HOT 1
- Async programming in simulation HOT 6
- BusSlaveFactory driveFlow does not honor byteEnable HOT 5
- how can i using axi stream fifo frame mode HOT 2
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from spinalhdl.