Comments (2)
It may be related to :
verilator/verilator#4424
from spinalhdl.
yes, that the exact same issue...
from spinalhdl.
Related Issues (20)
- Warn / prohibit using SlowArea clock wire HOT 4
- IMasterSlave type of Stream payload HOT 2
- How can I use "dophase" to check some diy list? HOT 6
- Axi4Stream user signal width should not be multiplied by data width HOT 1
- The wave reload question of VCS simulation HOT 5
- Is there any way to add delay at assignment? HOT 5
- Pipeline API `throwWhen(usingReady = true)` doesn't drop transaction when conflicting with prior `halt` HOT 1
- ClockDomain for input/output ports? HOT 10
- question about mem initialization HOT 11
- StreamFragmentWidthAdapter.make missing earlylast argument HOT 2
- How to generate RTL with parameters? HOT 2
- StreamMux with streamed select no correct join HOT 9
- WishboneSlaveFactory - doWrite is never called in pipelined mode HOT 3
- Wishbone BusIf SEL usage HOT 1
- Formal verifiation: SymbiYosys of SpinalTemplateSbt fails with "RG_WIDTH > 1 is not support by async2sync, use clk2fflogic." when using async reset
- Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys HOT 10
- Set clock domain from blackbox HOT 2
- Error when create a new ClockDomain in simulation HOT 2
- SystemVerilog Interface Support HOT 2
- NamedType returns null when called outside of a Component HOT 11
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from spinalhdl.