Comments (3)
Pushed fix to opencircuitdesign.com ; this will be updated in github overnight. I will close this tomorrow after the update.
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Thanks a lot! I'll provide a similar change for magic soon.
from netgen.
For me, doing "ldd /usr/local/lib/netgen/tcl/netgenexec" shows that libX11 is linked to the file, so I assume that there is no harm in doing this.
from netgen.
Related Issues (20)
- LVS issue when running on gf180mcu HOT 5
- gf180mcuC lvs mismatch HOT 5
- Missing circuit matching.
- SIGSEGV during verilog read for mgmt_core_wrapper HOT 2
- Altering port lists with duplicate ports causes incorrect connectivity HOT 7
- Unsymmetrical reduction of parameters causes size mismatch.
- Uninitialized count in pnp device count comparison HOT 9
- parallel/series reduction of resistor network yields size errors.
- JSON LVS Report doesn't match the text LVS report HOT 1
- Unable to launch netgen HOT 3
- Netlists created with ext2spice short resistor should be equivalent to those created without HOT 1
- Verilog ports shorted with assign statements in subcells are not handled correctly. HOT 7
- netgen doesn't handle attributes correctly or escapes inside escapes. HOT 2
- False negative errors HOT 3
- Using netgen to generate ".sim" files from ".spice" netlists HOT 24
- make install fails [tclnetgen.dylib] Error 1 HOT 3
- 'M' Property Error on Single PNP HOT 2
- Multiple ports connected with verilog assign do not match. HOT 4
- netcmp.c / MatchPins HOT 2
- `assign` doesn't handle implicitely created wires in the LHS
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