Comments (1)
Ultimately this issue appears to be both an issue in magic and an unrelated issue in netgen.
I have determined that the problem in netgen is that a shorting device like a zero-valued resistor or voltage source should never be removed to "make a better match" if it is connecting two ports together. Otherwise the ports get scrambled. Unscrambling them is a pain. It seems much better just to let the cell match fail in that case, get flattened, and try to resolve the zero-valued device in the next hierarchical level up. That continues until either the device does not connect to two ports, and can be safely removed and the nets merged, or until it reaches the top of the hierarchy, in which it can be treated as a port error, but there is no hierarchy above that can get affected by the mismatched ports.
With this change, the testcase referenced above in the issue in Magic ends up as a unique matching result.
The code fix is in netgen version 1.5.257.
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Related Issues (20)
- netgen module name size limited to 100 characters HOT 1
- LVS issue when running on gf180mcu HOT 5
- gf180mcuC lvs mismatch HOT 5
- Missing circuit matching.
- SIGSEGV during verilog read for mgmt_core_wrapper HOT 2
- Altering port lists with duplicate ports causes incorrect connectivity HOT 7
- Unsymmetrical reduction of parameters causes size mismatch.
- Uninitialized count in pnp device count comparison HOT 9
- parallel/series reduction of resistor network yields size errors.
- JSON LVS Report doesn't match the text LVS report HOT 1
- Unable to launch netgen HOT 3
- Verilog ports shorted with assign statements in subcells are not handled correctly. HOT 7
- netgen doesn't handle attributes correctly or escapes inside escapes. HOT 2
- False negative errors HOT 3
- Using netgen to generate ".sim" files from ".spice" netlists HOT 24
- make install fails [tclnetgen.dylib] Error 1 HOT 3
- 'M' Property Error on Single PNP HOT 2
- Multiple ports connected with verilog assign do not match. HOT 4
- netcmp.c / MatchPins HOT 2
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