• HSIZE explanation? (when useful)
• If HBURST > 0 and HSIZE < DSIZE, what happens with HADDR?

incorrect assignment of these bits can lead to incorrect system behavior.

The DECERR response indicates that the interconnect cannot successfully decode a Subordinate access.
If the interconnect cannot successfully decode a Subordinate access, it must return the DECERR response. This
specification recommends that the interconnect routes the access to a default Subordinate, and the default
Subordinate returns the DECERR response.
The AXI protocol requires that all data transfers for a transaction are completed, even if an error condition occurs.
Any component giving a DECERR response must meet this requirement.

Memory Subordinate

A Memory Subordinate is required to handle all transaction types correctly.

Peripheral Subordinate

A Peripheral Subordinate has an IMPLEMENTATION DEFINED method of access. Typically, the
method of access is defined in the component data sheet, that describes the transaction types that the
Subordinate handles correctly.
Any access to the Peripheral Subordinate that is not part of the IMPLEMENTATION DEFINED method
of access must complete, in compliance with the protocol. However, when such an access has been
made, there is no requirement that the Peripheral Subordinate continues to operate correctly. It is
only required to continue to complete further transactions in a protocol-compliant manner.

• https://semiengineering.com/when-does-my-soc-design-need-a-noc/
• https://www.theeeview.com/what-is-a-noc-in-an-fpga/
• https://www.edn.com/soc-design-when-is-a-network-on-chip-noc-not-enough/

AHB

The minimum address space that can be allocated to a single Subordinate is 1KB, and the start and the end of the
address region must exist on a 1KB boundary. All Managers are designed so that they do not perform incrementing
transfers over a 1KB address boundary. This ensures that a burst never crosses an address decode boundary.

AXI

The maximum size of a transaction is 4KB and transactions are not permitted to cross a 4KB boundary. However,
many Managers generate transactions which are guaranteed to be smaller than this.
A Subordinate or interconnect might benefit from this information. For example, a Subordinate might be able to
optimize away some decode logic. An interconnect striping at a granule smaller than 4KB might be able to avoid
burst splitting if it knows that transactions will not cross the stripe boundary.

• APB
• AHB
• AXI-Full
• AXI-Lite
• AXI-Stream
• Others

• AMBA spec's drawbacks
  • Missing waveforms (almost none for AXI4+)
  • Not real/modern examples
  • Features not well explained
• Addition of real-world considerations
• Others

• Split HREADY (IN) & HREADYOUT in all the waveforms (or maybe a waveform with a better explanation?)
• HREADY = HREADYOUT at the end (extra info)
• HSIZE explanation? (when useful)
• If HBURST > 1 and HSIZE < DSIZE, what happens with HADDR?
• Could HMASTLOCK explanation be improved?
• BUSY in WRAP4/INCR4? (maybe split?)
• HSEL should be HIGH when ADDR/CTRL latched, doesn't matter the rest of the time
• Remove HPROT from the first image?

AHB

Default Subordinate

If a system design does not contain a completely filled memory map, then an additional default Subordinate must
be implemented to provide a response when any of the nonexistent address locations are accessed.
If a NONSEQUENTIAL or SEQUENTIAL transfer is attempted to a nonexistent address location, then the default
Subordinate provides an ERROR response.
IDLE or BUSY transfers to nonexistent locations result in a zero wait state OKAY response.

AXI

DECERR, decode error

The DECERR response indicates that the interconnect cannot successfully decode a Subordinate access.
If the interconnect cannot successfully decode a Subordinate access, it must return the DECERR response. This
specification recommends that the interconnect routes the access to a default Subordinate, and the default
Subordinate returns the DECERR response.
The AXI protocol requires that all data transfers for a transaction are completed, even if an error condition occurs.
Any component giving a DECERR response must meet this requirement.

When a Manager generates a transfer that is narrower than its data bus, the address and control information
determine the byte lanes that the transfer uses:

• In incrementing or wrapping bursts, different byte lanes are used on each beat of the burst.
• In a fixed burst, the same byte lanes are used on each beat.

As a general principle, components must support all combinations of inputs, but do not have to generate all
combinations of outputs. For example, a Subordinate must support all the different possible lengths of burst, but a
Manager only has to generate the types of burst that it uses. This policy ensures that all components work with all
other components.

AXI supports unaligned transfers. For any burst that is made up of data transfers wider than 1 byte, the first bytes
accessed might be unaligned with the natural address boundary. For example, a 32-bit data packet that starts at a
byte address of 0x1002 is not aligned to the natural 32-bit address boundary.
A Manager can:

• Use the low-order address lines to signal an unaligned start address.
• Provide an aligned address and use the byte lane strobes to signal the unaligned start address.

Note
The information on the low-order address lines must be consistent with the information on the byte lane strobes.
The Subordinate is not required to take special action based on any alignment information from the Manager.