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The Svnapot extension says:

Invalid NAPOT encodings were chosen to raise page-fault exceptions rather than access-fault exceptions, following the convention that invalid PTE configurations result in page-faults exceptions, while invalid access types or accesses to invalid physical memory regions trigger page faults.

According to this statement, everything triggers a page fault. Perhaps this could say instead:

... following the convention that only violations of physical memory attributes and PMP raise access faults.

Just to make sure, as I understand it, is it like a nested page walk? Which means for example, up to 24 memory accesses for Sv48.

When execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U mode, Does it raise an illegal instruction exception?

The Svnapot extension says:

Implicit reads of NAPOT page table may create address-translation cache entries ...

I believe instead of "NAPOT page table" it means "NAPOT PTE". (If not, then "NAPOT page table" needs to be defined. I don't know what that would be.)

Given that all address translation pages are "naturally aligned power-of-two", including the pre-existing 4 kB ones, I'm not sure the name "NAPOT" really conveys well what is different about the PTE encodings added by the Svnapot extension.

A possible alternative term might be "umbrella PTE", reflecting how one such PTE covers the same address range as multiple 4-kB PTEs.

The Svpbmt draft says:

If the underlying physical memory attribute for a page is main memory and the page has PBMT=0 or PBMT=1, or if the underlying physical memory attribute for a page is I/O and the page has PBMT=2, then accesses to that page obey the same memory ordering rules normally applied to accesses to that physical page.

For the case that the underlying physical memory attribute for a page is I/O, shouldn't this sentence say "PBMT = 0 or PBMT = 2" instead of just "PBMT = 2"?

When executing in VU mode, attempts to execute SFENCE, SINVAL, HFENCE, and HINVAL instructions must all raise a virtual instruction exception. The Svinval draft currently says:

... an attempt to execute any of the above in U-mode or VU-mode
raises an illegal instruction exception.

Concerning VU mode, this statement is incorrect.

Hi,

Just spot this in the address-translation algorithm description just above the ending paragraphs of normative text. Sorry I can't find the source therefore can't really post a link to it. I supposed the "9" in the square brackets below only applies to SV32?

j[9 : napot_bits] = i[9 : napot_bits],

To make it generic enough to apply to SV39/SV48 etc, perhaps better to change it to vpn_bits-1 or simply vpn_msb?

Regards,
Freddie