Comments (4)
We are currently on commit e465de145c69c28230b5c73cc58f96fd9bd04419
while using commit cf7369999779bc78bcc5a8a6fe6187363b23247a
of the RISCV tools and have tried running thebbl both with and without payload.
When running the bbl without payload, everything works as expected and we get the following output:
This is bbl's dummy_payload. To boot a real kernel, reconfigure
bbl with the flag --with-payload=PATH, then rebuild bbl.
When running the bbl with a Linux kernel as a payload, spike
seems to hang (see attached spike trace file) where it used to segfault in the previous commit 75f2a05df9cdff6f3faba748065b3184b9f01b01
. We are actually using commit 9079be6167aec516a4625b7dcf20efbf384277b4
of the riscv-linux repository.
In case it is useful, the configuration line used to generate such bbl is the following:
../configure --prefix=path/to/riscv-tools/installation --host=riscv64-unknown-elf host_alias=riscv64-unknown-elf RISCV=path/to/riscv-tools/installation --with-payload=path/to/linux/vmlinux --disable-logo
If simulating a bbl with payload is working for you, would you mind telling me which precise commits of the repositories are you using?
In file spike_execution_trace.txt you can find a trace where a "full iteration" of spike is shown.
from riscv-isa-sim.
Since the segfault is fixed, I'm not sure what to do here. bbl works correctly for me.
from riscv-isa-sim.
Ah, so, it's not Spike that's hanging; the kernel or BBL is hanging. The question is, what causes the target software to jump to address 0?
FYI, I'm using the HEAD of the riscv-next branch of riscv-linux; HEAD of priv-1.10 of riscv-pk; and HEAD of priv-1.10 of riscv-isa-sim. That combination seems to work.
from riscv-isa-sim.
You are absolutely right, coming from an older build I was using the wrong branch of the riscv-linux repository. Thank you for your time. for pointing me to the right branches, and sorry for the confusion!
from riscv-isa-sim.
Related Issues (20)
- [BUG] instruction bugs for RV32 isa HOT 5
- Supporting variable XLEN HOT 3
- mseccfg useed and sseed bits cannot be modified when zkr is implemented
- [BUG] Spike incorrectly executes V extension instructions when vsstatus.vs is off and V=1. HOT 3
- frm is illegal value , a vector fp inst raise illegal inst but it still will make vs dirty HOT 1
- For the vfmv.v.f, fmv.w.x, fmv.x.w instructions, should spike consistently ignore the higher 32 bits when processing single-precision floating-point numbers? HOT 3
- mcontrol6.timing bit is set HOT 4
- Counter-intuitive MMIO device arguments behavior HOT 3
- reading mtinst gives illegal instruction exception HOT 1
- Spike setting VTYPE to 0x8000000000000000 for e16 mf8 HOT 1
- How can I read content from a file and use it as input for an ELF file HOT 4
- misa is not printed by the instruction csrrci HOT 1
- satp written with an unsupported MODE should have no effect HOT 7
- mstatus.fs cannot be written as initial HOT 2
- spike doesn't update sepc and stval in virtual address mode HOT 5
- Why misaligned store will raise store/amo access fault at the function store_slow_path? HOT 3
- Zfa extension instruction fcvtmod_w_d behavior conflict with sail model on too large/ too small boundary HOT 2
- Parse Zve/Zvl to determine RVV settings, instead of --varch HOT 1
- Build fails with "error: 'L_tmpnam' was not declared in this scope" HOT 4
- for vl=0 does vfredsum need to make vd[0]=vs1[0]? HOT 1
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from riscv-isa-sim.