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A OpenCL-based FPGA benchmark suite for HPC

License: MIT License

CMake 5.30% C 41.24% C++ 49.98% Shell 1.07% Python 1.70% Jupyter Notebook 0.70% Tcl 0.01%

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hpcc_fpga's Issues

Building on AWS F1 instance

Hello,

I'm trying to build HPCC_FPGA on AWS using an F1 instance.
I tried both with "FPGA Developer AMI (Centos 7)" and "FPGA Developer AMI (Amazon Linux 2)" with GCC 10 but during cmake execution I got some errors:

Looking for pthread_create in pthreads - not found
ERROR Xilinx Vitis or Intel FPGA OpenCL SDK required!

I sourced all required environment scripts so the vitis_hls command is found:
which vitis_hls
/opt/Xilinx/Vitis_HLS/2020.2/bin/vitis_hls

What OS did you use to build?

Thanks.

STREAM benchmark: failed to load xclbin: Invalid argument

I am trying to get one of these benchmarks working on the Noctua2 system. When I build the emulated kernel and attempt to run, I get the following output:

-------------------------------------------------------------
General setup:
C++ high resolution clock is used.
The clock precision seems to be 1.00000e+01ns
-------------------------------------------------------------
Selected Platform: Xilinx
Multiple devices have been found. Select the device by typing a number:
0) xilinx_u280_xdma_201920_3
1) xilinx_u280_xdma_201920_3
2) xilinx_u280_xdma_201920_3
Enter device id [0-2]:0
-------------------------------------------------------------
Selection summary:
Platform Name: Xilinx
Device Name:   xilinx_u280_xdma_201920_3
-------------------------------------------------------------
-------------------------------------------------------------
FPGA Setup:./bin/stream_kernels_single_emulate.xclbin
XRT build version: 2.12.429
Build hash: 2180e838abe791cb1e90d9011bbc8b3676774172
Build date: 2022-04-08 11:43:35
Git branch: 2021.2_RHEL8.5
PID: 1159967
UID: 92395
[Mon Dec 19 17:29:04 2022 GMT]
HOST: n2fpga14
EXE: /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/STREAM/build/bin/STREAM_FPGA_xilinx
[XRT] ERROR: See dmesg log for details. err=-2
[XRT] ERROR: failed to load xclbin: Invalid argument
ERROR in OpenCL library detected! Aborting.
/upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/shared/setup/fpga_setup.cpp:168: CL_OUT_OF_HOST_MEMORY
An error occured while setting up the benchmark: 
	An OpenCL error occured: CL_OUT_OF_HOST_MEMORY
Benchmark execution started without successfully running the benchmark setup!

These are the steps I'm taking to build and run the benchmark:

cd STREAM
mkdir build
cd build
cmake .. -DVitis_INCLUDE_DIRS=/opt/software/FPGA/Xilinx/Vitis/2021.2/include -DVitis_FLOATING_POINT_LIBRARY=/opt/software/FPGA/Xilinx/Vitis_HLS/2022.1/lnx64/tools/fpo_v7_0/libIp_floating_point_v7_0_bitacc_cmodel.so  -DHPCC_FPGA_CONFIG=$PWD/../configs/Xilinx_U280_DP.cmake -DMPI_C=$HOME/repos/mvapich2/install/lib/libmpi.so -DMPI_CXX=$HOME/repos/mvapich2/install/lib/libmpi.so
make all
CL_CONTEXT_EMULATOR_DEVICE=1 srun -p fpga -N 1 --constraint=xilinx_u280_xrt2.12 -t 00:30:00 ./bin/STREAM_FPGA_test_xilinx -f ./bin/stream_kernels_single_emulate.xclbin

Software versions:
XRT: v2.12
Vitis: v21.2
Device Platform: u280_xdma_201920_3_3246211
HPCC_FPGA: v0.5.1

It seems as if the xclbin is not being generated correctly. Am I missing a build step or is this a bug in the build?

Memory binding error with STREAM and RandomAccess

Hi,
I tried compiling and running the STREAM and RandomAccess benchmarks for the BittWare 520N-MX platform which has a Stratix 10 MX FPGA.
For both benchmarks, configuration options were set to their respective default values.
While running the benchmarks, I receive the following error:
acl_mem.cpp:333: int acl_bind_buffer_to_device(cl_device_id, cl_mem): Assertion 'mem' failed.

I couldn't find any resources online to debug this. Please help me with this.

LINPACK on Xilinx U280: invalid port or argument name: m_axi_gmem0

I am attempting to build the torus kernel for the LINPACK benchmark, but the build errors out in the link stage due to an invalid port mapping. I'm not sure I understand why this issue is occuring, but my guess would be that the m_axi_gmemX ports are expected to be specified within the kernel. This error seems to imply the final kernel code is not being generated correctly. Is there a setting in my build that is missing? I expected the config file to take care of most of the gotchas, since U280s seem to be supported by the benchmark.

cd LINPACK
mkdir build
cd build
cmake .. -DVitis_INCLUDE_DIRS=/opt/software/FPGA/Xilinx/Vitis/2021.2/include -DVitis_FLOATING_POINT_LIBRARY=/opt/software/FPGA/Xilinx/Vitis_HLS/2021.2/lnx64/tools/fpo_v7_0/libIp_floating_point_v7_0_bitacc_cmodel.so -DHPCC_FPGA_CONFIG=../configs/Xilinx_U280_B8_SB3_R2.cmake -DMPI_C=$HOME/repos/mvapich2/install/lib/libmpi.so -DMPI_CXX=$HOME/repos/mvapich2/install/lib/libmpi.so
make hpl_torus_PCIE_xilinx
...
[ 50%] Generating ../../bin/hpl_torus_PCIE.xclbin
WARNING: [v++ 60-1600] The option 'jobs' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'hls.jobs', 'vivado.synth.jobs' in a configuration file. 
Option Map File Used: '/opt/software/FPGA/Xilinx/Vitis/2021.2/data/vitis/vpp/optMap.xml'

****** v++ v2021.2 (64-bit)
  **** SW Build 3363252 on 2021-10-14-04:41:01
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/bin/xilinx_reports/link
	Log files: /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/bin/xilinx_reports/logs/link
Running Dispatch Server on port: 34327
INFO: [v++ 60-1548] Creating build summary session with primary output /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/bin/hpl_torus_PCIE.xclbin.link_summary, at Tue Dec 20 16:47:58 2022
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Tue Dec 20 16:47:58 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/bin/xilinx_reports/link/v++_link_hpl_torus_PCIE_guidance.html', at Tue Dec 20 16:47:59 2022
INFO: [v++ 60-895]   Target platform: /opt/software/FPGA/Xilinx/platforms/xilinx_u280_xdma_201920_3_3246211/xilinx_u280_xdma_201920_3.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/software/FPGA/Xilinx/platforms/xilinx_u280_xdma_201920_3_3246211/hw/xilinx_u280_xdma_201920_3.xsa'
INFO: [v++ 74-78] Compiler Version string: 2021.2
INFO: [v++ 60-1302] Platform 'xilinx_u280_xdma_201920_3.xpfm' has been explicitly enabled for this release.
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_u280_xdma_201920_3
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [16:48:13] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/xilinx_tmp_compile/hpl_torus_PCIE.xo --config /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/int/syslinkConfig.ini --xpfm /opt/software/FPGA/Xilinx/platforms/xilinx_u280_xdma_201920_3_3246211/xilinx_u280_xdma_201920_3.xpfm --target hw --output_dir /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/int --temp_dir /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link
INFO: [v++ 60-1454] Run Directory: /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Tue Dec 20 16:48:14 2022
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/xilinx_tmp_compile/hpl_torus_PCIE.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [16:48:27] build_xd_ip_db started: /opt/software/FPGA/Xilinx/Vitis/2021.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/xilinx_u280_xdma_201920_3.hpfm -clkid 0 -ip /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/iprepo/xilinx_com_hls_lu_1_0,lu -ip /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/iprepo/xilinx_com_hls_top_update_1_0,top_update -ip /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/iprepo/xilinx_com_hls_inner_update_mm0_1_0,inner_update_mm0 -ip /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/iprepo/xilinx_com_hls_left_update_1_0,left_update -o /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [16:48:32] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2369.379 ; gain = 0.000 ; free physical = 392220 ; free virtual = 422552
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [16:48:32] cfgen started: /opt/software/FPGA/Xilinx/Vitis/2021.2/bin/cfgen  -nk lu:1 -nk left_update:1 -nk top_update:1 -nk inner_update_mm0:2 -slr lu_1:SLR0 -slr left_update_1:SLR0 -slr top_update_1:SLR0 -slr inner_update_mm0_1:SLR1 -slr inner_update_mm0_2:SLR2 -sp lu_1.m_axi_gmem0:DDR[0] -sp lu_1.m_axi_gmem1:DDR[0] -sp lu_1.m_axi_gmem2:DDR[1] -sp top_update_1.m_axi_gmem0:DDR[0] -sp top_update_1.m_axi_gmem1:DDR[0] -sp top_update_1.m_axi_gmem2:DDR[0] -sp left_update_1.m_axi_gmem0:DDR[0] -sp left_update_1.m_axi_gmem1:DDR[1] -sp left_update_1.m_axi_gmem2:DDR[1] -sp inner_update_mm0_1.m_axi_gmem0:DDR[0] -sp inner_update_mm0_1.m_axi_gmem1:DDR[1] -sp inner_update_mm0_1.m_axi_gmem2:DDR[0] -sp inner_update_mm0_2.m_axi_gmem0:DDR[0] -sp inner_update_mm0_2.m_axi_gmem1:DDR[1] -sp inner_update_mm0_2.m_axi_gmem2:DDR[0] -dmclkid 0 -r /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: lu, num: 1  {lu_1}
INFO: [CFGEN 83-0]   kernel: left_update, num: 1  {left_update_1}
INFO: [CFGEN 83-0]   kernel: top_update, num: 1  {top_update_1}
INFO: [CFGEN 83-0]   kernel: inner_update_mm0, num: 2  {inner_update_mm0_1 inner_update_mm0_2}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: lu_1, k_port: m_axi_gmem0, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: lu_1, k_port: m_axi_gmem1, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: lu_1, k_port: m_axi_gmem2, sptag: DDR[1]
INFO: [CFGEN 83-0]   kernel: top_update_1, k_port: m_axi_gmem0, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: top_update_1, k_port: m_axi_gmem1, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: top_update_1, k_port: m_axi_gmem2, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: left_update_1, k_port: m_axi_gmem0, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: left_update_1, k_port: m_axi_gmem1, sptag: DDR[1]
INFO: [CFGEN 83-0]   kernel: left_update_1, k_port: m_axi_gmem2, sptag: DDR[1]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_1, k_port: m_axi_gmem0, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_1, k_port: m_axi_gmem1, sptag: DDR[1]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_1, k_port: m_axi_gmem2, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_2, k_port: m_axi_gmem0, sptag: DDR[0]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_2, k_port: m_axi_gmem1, sptag: DDR[1]
INFO: [CFGEN 83-0]   kernel: inner_update_mm0_2, k_port: m_axi_gmem2, sptag: DDR[0]
INFO: [CFGEN 83-0] SLR Specs: 
INFO: [CFGEN 83-0]   instance: inner_update_mm0_1, SLR: SLR1
INFO: [CFGEN 83-0]   instance: inner_update_mm0_2, SLR: SLR2
INFO: [CFGEN 83-0]   instance: left_update_1, SLR: SLR0
INFO: [CFGEN 83-0]   instance: lu_1, SLR: SLR0
INFO: [CFGEN 83-0]   instance: top_update_1, SLR: SLR0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem1
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem2
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem1
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem2
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem1
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem2
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem1
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem2
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem0
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem1
ERROR: [CFGEN 83-2292] --sp tag applied to an invalid port or argument name: m_axi_gmem2
ERROR: [CFGEN 83-2298] Exiting due to previous error
ERROR: [SYSTEM_LINK 82-36] [16:48:35] cfgen failed
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2369.379 ; gain = 0.000 ; free physical = 391997 ; free virtual = 422329
ERROR: [SYSTEM_LINK 82-62] Error generating design file for /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /opt/software/FPGA/Xilinx/Vitis/2021.2/bin/cfgen  -nk lu:1 -nk left_update:1 -nk top_update:1 -nk inner_update_mm0:2 -slr lu_1:SLR0 -slr left_update_1:SLR0 -slr top_update_1:SLR0 -slr inner_update_mm0_1:SLR1 -slr inner_update_mm0_2:SLR2 -sp lu_1.m_axi_gmem0:DDR[0] -sp lu_1.m_axi_gmem1:DDR[0] -sp lu_1.m_axi_gmem2:DDR[1] -sp top_update_1.m_axi_gmem0:DDR[0] -sp top_update_1.m_axi_gmem1:DDR[0] -sp top_update_1.m_axi_gmem2:DDR[0] -sp left_update_1.m_axi_gmem0:DDR[0] -sp left_update_1.m_axi_gmem1:DDR[1] -sp left_update_1.m_axi_gmem2:DDR[1] -sp inner_update_mm0_1.m_axi_gmem0:DDR[0] -sp inner_update_mm0_1.m_axi_gmem1:DDR[1] -sp inner_update_mm0_1.m_axi_gmem2:DDR[0] -sp inner_update_mm0_2.m_axi_gmem0:DDR[0] -sp inner_update_mm0_2.m_axi_gmem1:DDR[1] -sp inner_update_mm0_2.m_axi_gmem2:DDR[0] -dmclkid 0 -r /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /upb/departments/pc2/users/m/mpifpga2/repos/HPCC_FPGA/LINPACK/build/src/device/_x/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [16:48:35] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 2265.199 ; gain = 0.000 ; free physical = 392006 ; free virtual = 422334
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make[3]: *** [src/device/CMakeFiles/hpl_torus_PCIE_xilinx.dir/build.make:75: bin/hpl_torus_PCIE.xclbin] Error 1
make[2]: *** [CMakeFiles/Makefile2:501: src/device/CMakeFiles/hpl_torus_PCIE_xilinx.dir/all] Error 2
make[1]: *** [CMakeFiles/Makefile2:508: src/device/CMakeFiles/hpl_torus_PCIE_xilinx.dir/rule] Error 2
make: *** [Makefile:283: hpl_torus_PCIE_xilinx] Error 2

Error while building RandomAccess benchmark

Hi,

I am trying to build and test the RandomAccess benchmark for the Nallatech 520N card. After following the steps outlined in the README and running make all, I get the following output:

Scanning dependencies of target hpcc_fpga_base
[ 4%] Building CXX object lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/setup/fpga_setup.cpp.o
In file included from /home/UFAD/g.ramesh/HPCC_FPGA/shared/include/setup/fpga_setup.hpp:36:0,
from /home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:5:
/tools/Intel/quartus_pro/19.4.0.64/hld/host/include/CL/cl.hpp:155:110: note: #pragma message: This version of the OpenCL Host API C++ bindings is deprecated, please use cl2.hpp instead.
#pragma message("This version of the OpenCL Host API C++ bindings is deprecated, please use cl2.hpp instead.")
^
In file included from /home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:5:0:
/home/UFAD/g.ramesh/HPCC_FPGA/shared/include/setup/fpga_setup.hpp:130:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Program
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/include/setup/fpga_setup.hpp:156:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Device
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:129:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Program
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:213:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Device
^
make[2]: *** [lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/setup/fpga_setup.cpp.o] Error 1
make[1]: *** [lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/all] Error 2
make: *** [all] Error 2

Consequently, I made the following changes to the file "fpga_setup.hpp" located at "HPCC_FPGA/shared/include/setup/"

Added the following preprocessor macros:
#define CL_HPP_TARGET_OPENCL_VERSION 120
#define CL_HPP_MINIMUM_OPENCL_VERSION 120
Changed the included header file from #include "CL/cl.hpp" to #include "CL/cl2.hpp"

Ran the make clean && make all to get this output:

[ 4%] Building CXX object lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/setup/fpga_setup.cpp.o
In file included from /home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:5:0:
/home/UFAD/g.ramesh/HPCC_FPGA/shared/include/setup/fpga_setup.hpp:130:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Program
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/include/setup/fpga_setup.hpp:156:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Device
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:129:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Program
^
/home/UFAD/g.ramesh/HPCC_FPGA/shared/setup/fpga_setup.cpp:213:5: error: ‘unique_ptr’ in namespace ‘std’ does not name a type
std::unique_ptrcl::Device
^
make[2]: *** [lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/setup/fpga_setup.cpp.o] Error 1
make[1]: *** [lib/hpccbase/CMakeFiles/hpcc_fpga_base.dir/all] Error 2
make: *** [all] Error 2

I am unable to figure out the solution to this error. Please help me.

Relevant details:
OS: CentOS Linux 7
Cmake version: 3.17.3
Python3 not installed

Error with buffer creation in FFT benchmark

Hi,

When the FFT benchmark is configured with NUM_REPLICATIONS > 4, the make CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 test command fails with the following message:

Error: Invalid or unsupported flags
ERROR in OpenCL library detected! Aborting.
<root_dir>/FFT/src/host/execution_default.cpp:66: CL_INVALID_VALUE
An error occured while executing the benchmark:
An OpenCL error occured: CL_INVALID_VALUE

This is the code causing the error:

HPCC_FPGA/FFT/src/host/execution_default.cpp

Lines 65 to 66 in 484d9f6

 outBuffers.push_back(cl::Buffer(*config.context, CL_MEM_WRITE_ONLY | (config.programSettings->useMemoryInterleaving ? 0 : (((2 * r) + 2) << 16)), (1 << LOG_FFT_SIZE) * iterations_per_kernel * 2 * sizeof(HOST_DATA_TYPE), NULL, &err)); 

 ASSERT_CL(err)

The error seems to arise from the flag value, CL_MEM_WRITE_ONLY | (config.programSettings->useMemoryInterleaving ? 0 : (((2 * r) + 2) << 16)). I am curious about the purpose of the ((2 * r) + 2) << 16 operation and how it relates to the memory flag.

Any inputs regarding the error and potential ways to fix it will be hugely appreciated.

Thank you.

Supported devices

Hello,
while trying to compile the GEMM benchmark I get the following linking error:
INFO: [v++ 60-423] Target device: zcu106_base ERROR: [v++ 60-1139] Failed to parse --slr option: SLRs are not available in the specified platform.
Is is possible that my platform is not supported? If so, there's something that I can do about it?
Thanks

cl.hpp missing - OpenCL version mismatch?

Hello everyone,
I was trying to run the GEMM benchmark, cmake configuration succeeds but building fails with error CL/cl.hpp, no such file or directory. In my /usr/include/CL directory i don't have such file. May this be due to a mismatch in our OpenCL versions? My cl2.hpp file mentions version 2.0.7.
I have also trying setting USE_DEPRECATED_CPP_HEADER to false, in this case it fails with a sintax error in cl2.hpp, line 7841, expected ; at the end of method declaration.
Thanks
Pietro

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	outBuffers.push_back(cl::Buffer(config.context, CL_MEM_WRITE_ONLY \| (config.programSettings->useMemoryInterleaving ? 0 : (((2 r) + 2) << 16)), (1 << LOG_FFT_SIZE) * iterations_per_kernel * 2 * sizeof(HOST_DATA_TYPE), NULL, &err));
	ASSERT_CL(err)