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【ysyx第六期】关于L1 cache的实现限制和流片要求
动机
我希望实现cache,并且尽可能和流片要求一致。
考虑到ysyx第六期的cache
相关的文档和SoC
基建似乎并未完成,当前已经有不少同学参照第五期进行cache等后续模块的开发。所以希望了解下,第六期中cache的实现限制和流片要求。
想法和实现
- 如果在
IFU
和LSU
内分别实现L1 instruction cache (L1I)
和L1 data cache (L1D)
,这样的cache
实现位于核内,对ysyxSoC
透明。那么存在的问题就是,核内cache
的必然是用reg
实现,那么会增加流片的面积,那么流片时是否对核心的总reg
数目有限制?或者说L1I+L1D
的总大小需要限制在多少以内? (感谢 @chaoyulong 分享的想法和讨论)
IFU -> IDU -> EXU -> LSU
^ ^
| v
- - - - BUS - - - -
^ AXI4
v
ysyxSoC[SRAM,flash,SDRAM]
- 利用
ysyxSoC
中的SRAM
来实现cache
,需要修改核心和SoC
的总线,和SRAM
的控制器。第六期是否会采用这种方式?如果提前使用这种方式来进行开发,有什么建议以便和ysyxSoC
未来的更新合并?
Could ysyx team provide the source code of RT-Thread binary?
Currently I'm looking at the source code here (https://github.com/OSCPU/rt-thread), but the C source code doesn't match with the assembly, e.g., rt_thread_idle_entry
function differs in the source code and in the binary. It would greatly help for debugging if ysyx team gives the source code of the modified version of RT-Thread. Thanks!
关于串口行为模型与讲义预期行为不一致的问题
讲义中提到,如果不正确设置除数寄存器,会导致串口只输出前16个字符的内容。但在rtl代码中,字符串的打印是通过uart_tfifo.v第209行代码的if (push) $write("%c", data_in);实现的。这会导致只要产生输入数据的push信号,就会直接将字符串打印至终端。而rtl模型并未对tx的错误信号进行处理,因此也不会阻塞状态机的执行,程序表现仍然如同无误。
为了修正这个问题,需要添加判断该数据执行push的时候,是否会导致溢出的判断条件,即修改为if (push & !(count==fifo_depth)) $write("%c", data_in);新增的判断条件与反转overrun信号的条件一致,表示该数据导致了fifo的溢出。添加该条件以后,可以复现讲义中提到的问题。
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