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abstract-machine

A minimal, modularized, and machine-independent hardware abstraction layer

aljabr-1

Methods in Algebra (Volume 1): A Chinese textbook on Algebra

am-kernels

AbstractMachine kernels

arith64

__udivdi3(), __divdi3(), __umoddi3(), __moddi3(), etc. for embedded GCC

chisel3

Chisel 3: A Modern Hardware Design Language

cmdline

A Command Line Parser

difftest

drawio-desktop

Official electron build of draw.io

firrtl

Flexible Intermediate Representation for RTL

ics-pa

The wrapper repo for NJU ICS PA.

ics-workbench

latex-template

lenet5-mnist-pytorch

The simplest implementation of LeNet5 with mnist in PyTorch. Accuracy: ~99%

nemu

nutshell

RISC-V SoC designed by students in UCAS

oscpu-framework

A Verilator-based demo.

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-dejagnu

DejaGnu RISC-V port

riscv-gcc

riscv-tests

rt-thread

RT-Thread is an open source IoT operating system.

runcat_for_windows

A cute running cat animation on your windows taskbar.

rvcc

本课程基于Rui的chibicc，@sunshaoce和@ksco将其由原来的X86架构改写为RISC-V 64架构，同时加入了大量的中文注释，并且配有316节对应于每一个commit的课程，帮助读者可以层层推进、逐步深入的学习编译器的构造。

rvcc-course

uint128_t

C++ unsigned 128 bit integer type

uint256_t

C++ unsigned 256 bit integer type

verilator

Verilator open-source SystemVerilog simulator and lint system

ysyx-workbench

ysyxsoc

yuquan

A RISC-V core running Debian.