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VHDL compiler and simulator

License: GNU General Public License v3.0

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vhdl simulator compiler fpga

nvc's Introduction

Synopsis

NVC is a VHDL compiler and simulator.

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for VHDL-2019 is under development.

NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code.

NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard.

NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Usage

Simulating a VHDL hardware design involves three steps: analysing the source files; elaborating the design; and running the simulation. This is analogous to compiling, linking, and executing a software program. With NVC these steps are accomplished using the -a, -e, and -r commands:

$ nvc -a my_design.vhd my_tb.vhd
$ nvc -e my_tb
$ nvc -r my_tb

Or more succinctly, as a single command:

$ nvc -a my_design.vhd my_tb.vhd -e my_tb -r

Where my_tb is the name of the top-level test-bench entity.

The full manual can be read after installation using man nvc or online.

License

This program is free software distributed under the terms of the GNU General Public License version 3 or later. You may use, modify, and redistribute the program as you wish but if you distribute modifications you must preserve the license text and copyright notices, and also make the modified source code available to your users.

The source files for the IEEE standard libraries are included in the repository. These were originally provided under a proprietary license that forbid distribution of modifications, but in 2019 were relicensed under Apache 2.0. Freely redistributable versions of the 1993 libraries were made by editing and removing declarations from the 2019 libraries, and so are also licensed under Apache 2.0. Certain VHDL libraries developed specifically for NVC under lib/nvc and lib/std are also licensed under Apache 2.0. See the individual files for details.

The VITAL libraries are distributed under lib/vital. These were derived from draft copies of the packages freely available on the internet. The license status of these is unclear as the final text is part of the VITAL standard which must be purchased from the IEEE. If you are packaging this program for a distribution with strict free software requirements you should strip these files from the tarball and configure with --disable-vital.

Installing

NVC is developed under GNU/Linux and is regularly tested on macOS and Windows under MSYS2.

On macOS NVC can be installed with brew install nvc. NVC is also packaged for FreeBSD, Gentoo, Arch Linux AUR, and several other distributions. A Windows installer is available from the releases page. Users of systems without existing packages should build from source.

NVC has both a release branch and a development master branch. The master branch should be stable enough for day-to-day use and has comprehensive regression tests, but the release branch is more suitable for third party packaging. The latest released version is 1.12.1. Significant changes since the last release are detailed in NEWS.md.

If you are building from a Git clone rather than a released tarball you first need to generate the configure script using:

./autogen.sh

In-tree builds are not supported so create a separate build directory:

mkdir build && cd build

Finally build and install using the standard autotools steps:

../configure
make
sudo make install

To use a specific version of LLVM add --with-llvm=/path/to/llvm-config to the configure command. The minimum supported LLVM version is 8.0. Versions between 8 and 16 have all been tested.

NVC also depends on Flex to generate the lexical analyser.

On a Debian derivative the following should be sufficient to install all required dependencies:

sudo apt-get install build-essential automake autoconf \
  flex check llvm-dev pkg-config zlib1g-dev libdw-dev \
  libffi-dev libzstd-dev

Only the MSYS2 environment on Windows is supported. The required dependencies can be installed with:

pacman -S base-devel mingw-w64-x86_64-{llvm,ncurses,libffi,check,pkg-config,zstd}

GtkWave can be used to view simulation waveforms. Version 3.3.79 or later is required for the default FST format.

Testing

To run the regression tests:

make check

The unit tests require the check library.

Reporting bugs

Report bugs to [email protected] or using the GitHub issue tracker. Please include enough information to reproduce the problem, ideally with a small VHDL test case. Issue #412 is a good example.

Please remember that this software is provided to you with NO WARRANTY and no expectation of support, but I will do my best to help with any issues you encounter.

Contributing

Patches can be sent as either pull requests on GitHub or by email using git --send-email. Please note however that as this is purely a spare-time hobby project for me, I have limited time available to review patches. All code submitted must follow the guidelines in contrib/STYLE.md.

I will not accept patches that add new copyright owners under src/. This is to ensure there is clear legal ownership should, for example, the license need to be updated. Significant contributors are instead listed in THANKS.md.

Language Support

VHDL standard revisions are commonly referred to by the year they were published. For example IEEE 1076-2008 is known as VHDL-2008. The default standard in NVC is currently VHDL-2008 but this can be changed with the --std argument. For example --std=1993 selects the VHDL-1993 standard.

The 1993, 2000, and 2002 revisions of the standard are fully supported. Please raise bugs for any missing or incorrectly implemented features you encounter. The current status of VHDL-2008 and VHDL-2019 support can be found on the features page.

VHPI

The VHDL standard contains a comprehensive API called VHPI for interfacing with foreign code written in C or another language. NVC implements a subset of VHPI sufficient for running cocotb. Refer to the manual for more information.

Vendor Libraries

NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors.

For OSVVM use nvc --install osvvm
For UVVM use nvc --install uvvm
For Xilinx ISE use nvc --install ise
For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl if you require simulation models of the XPM macros
For Altera Quartus use nvc --install quartus
For Lattice iCEcube2 use nvc --install icecube2
For Free Model Foundry common packages use nvc --install fmf

The libraries will be installed under ~/.nvc/lib.

nvc's People

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nvc's Issues

recursive constant assignment issue

The following code leads to Invalid operands for select instruction (LLVM):

library ieee;
use ieee.std_logic_1164.all;

package test5 is
constant c0: std_logic_vector(7 downto 0) := "10101010";
type t_array is array (1 downto 0) of std_logic_vector(7 downto 0);
constant c1 : t_array := (
1 => c0, --error
-- 1 => "10101010", --ok
0 => "10101010");

end test5;

expression cannot be folded

Thanks a lot for fixing the last issue. Now a very ugly one:
library ieee;
use ieee.std_logic_1164.all;

entity comp6_bot is
generic (num : integer := 2 );
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp6_bot is

function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 loop
tmp := tmp + val;
end loop;
return tmp;
end function cfunc;

constant cnum : integer := cfunc(num);
type m_a_t is array (cnum-1 downto 0) of std_logic_vector(num-1 downto 0);
signal ma : m_a_t;

begin
y <= x;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity comp6 is
end entity;

architecture rtl of comp6 is
signal b: std_logic_vector(7 downto 0);

component comp6_bot is
    generic (num : integer := 2 ); 
    port (
        y : out std_logic_vector(7 downto 0);
        x : in std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp6_bot
generic map (num => 8)  
    port map ( x=>x"aa", y=>b );

end architecture;

using enumaration type in loop_parameter_specification

VHDL-1993 allows to use enumaration type in loop_parameter_specification.

loop_statement ::= 
 [ loop_label : ]
 [ iteration_scheme ] loop
  sequence_of_statements
  end loop [ loop_label ] ;

iteration_scheme ::=
 while condition
 | for loop_parameter_specification

parameter_specification ::=
 identifier in discrete_range

discrete_range ::= discrete_subtype_indication | range

subtype_indication ::=
 [ resolution_function_name ] type_mark [ constraint ]

type_mark ::=
 type_name
 | subtype_name

w/ proposed issueZ,

entity issueZ is
begin
end entity issueZ;

architecture a of issueZ is
    type t is (e0, e1, e2, e3);
begin
    p : process
    begin
        f : for v in t loop
            report t'image(v);
        end loop f;
        wait;
    end process p;
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueZ.vhd
** Error: invalid range expression
        File test/regress/issueZ.vhd, Line 10
      f : for v in t loop
                   ^

cannot handle tree kind T_ARRAY_SLICE in rewrite refs

Resizing at instanciating not possible:
library ieee;
use ieee.std_logic_1164.all;

entity comp5_bot is
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp5_bot is
begin
y <= x;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity comp5 is
end entity;

architecture rtl of comp5 is
signal b: std_logic_vector(7 downto 0);
constant c: std_logic_vector(8 downto 0):=(others => '1');
component comp5_bot is
port (
y : out std_logic_vector(7 downto 0);
x : in std_logic_vector(7 downto 0) );
end component;
begin

c1: component comp5_bot
    port map ( x=>c(7 downto 0), y=>b );

end architecture;

cannot generate code for builtin identity

w/ proposed regression issueX,

package p is
    procedure pp (
        constant c : integer
    );
end package p;

package body p is
    procedure pp (
        constant c : integer
    ) is
        variable v : integer range -c to +c;
    begin
        v := 0;
    end procedure pp;
end package body p;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueX.vhd
** Fatal: cannot generate code for builtin identity

Error running regression code wait6.vhd with option --vcd.

Commit from 10.3.13:
nvc -r wait6 --vcd=wait6.vcd
results in
assertation "t->n-attrs<MAX_ATTRS" failed
General problem with bit_vector? Same behaviour with signal4.vhd.

codegen fails if deferred constant via function hidden in package body is used

w/ proposed regression issueH,

package issueH is
    constant c : bit_vector;
end package issueH;

package body issueH is
    pure function f (
        i : bit_vector;
        l : integer range 1 to integer'high
    ) return bit_vector is
        variable v : bit_vector(i'length-1 downto 0);
    begin
        v := i;
        return v(l-1 downto 0);
    end function f;
    constant c : bit_vector := f(X"1F", 5);
end package body issueH;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueH.vhd
[no error]

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc --codegen issueH
/usr/bin/opt -O2 -o /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.bc /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.bc
/usr/bin/llc -relocation-model=pic /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.bc
/usr/bin/gcc -shared -Wl,--export-all-symbols -Wl,--out-implib=/home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.a -o /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.so /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEH.s -L./src -lnvcimp
/tmp/ccVxpSae.o:fake:(.text+0x3a): undefined reference to `WORK.ISSUEH.F$STD.STANDARD.BIT_VECTOR$STD.STANDARD.INTEGER_return_STD.STANDARD.BIT_VECTOR'
collect2: error: ld returned 1 exit status
** Fatal: /usr/bin/gcc failed with status 256

address resolvement at nvc -r stage not possible

The following code leads to LLVM-error (cygwin):
LLVM error: could not resolve external global address:WIDTH

entity reg is
generic(
width: integer:=32
);
port(
clk: in bit;
regdata_i: in bit_vector(width-1 downto 0);
regdata_o: out bit_vector(width-1 downto 0)
);
end entity;

architecture rtl of reg is
signal reg: bit_vector(width-1 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
reg<=regdata_i;
end if;
end process;
regdata_o<=reg;
end rtl;

entity testreg is
end entity;

architecture rtl of testreg is
component reg is
generic(
width: integer:=32
);
port(
clk: in bit;
regdata_i: in bit_vector(width-1 downto 0);
regdata_o: out bit_vector(width-1 downto 0)
);
end component;
signal clk:bit;
begin

genclk: process begin
clk <= '1';
wait for 1 us;
clk <= '0';
wait for 1 us;
end process;

r1:reg
generic map(width=>8)
port map(clk=>clk,regdata_i=>x"ff");
end architecture;

generic mapping via aggregate using record constant raises SIGSEGV at ident.c:106

w/ proposed regression issueG,

entity comp is
    generic (g : bit_vector := "0");
begin
end entity comp;

architecture a of comp is
begin
end architecture a;

entity issueG is
begin
end entity issueG;

architecture a of issueG is
    type t is record
        g : bit;
    end record t;
    constant c : t := (
        g => '0'
    );
    component comp is
        generic (g : bit_vector := "0");
    end component comp;
begin
    u : comp
    generic map (g => (1 downto 0 => c.g));
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueG.vhd
Segmentation fault (core dumped)

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src gdb ./src/nvc.exe
[SNIP]
Reading symbols from /home/hiyuh/git-repos/nvc/src/nvc.exe...done.
(gdb) r -a test/regress/issueG.vhd
Starting program: /home/hiyuh/git-repos/nvc/src/nvc.exe -a test/regress/issueG.vhd
[New Thread 9452.0x2520]
[New Thread 9452.0x1d8c]

Program received signal SIGSEGV, Segmentation fault.
0x00440e45 in search_node (ch=117 'u', t=0x4b2c14 <root>) at ident.c:106
106     static struct clist *search_node(struct trie *t, char ch)
(gdb) bt
#0  0x00440e45 in search_node (ch=117 'u', t=0x4b2c14 <root>) at ident.c:106
#1  0x00441007 in search_trie (str=str@entry=0x93070, t=t@entry=0x4b2c14 <root>, end=end@entry=0x9305c) at ident.c:122
#2  0x004412a4 in ident_new (str=str@entry=0x4bfd89 <LOC_INVALID+2601> "unconstrained") at ident.c:146
#3  0x004197e3 in sem_locally_static (t=<optimized out>) at sem.c:4915
#4  0x00419797 in sem_locally_static (t=t@entry=0x801687d8) at sem.c:4860
#5  0x00419c27 in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5017
#6  0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#7  0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#8  0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#9  0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#10 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#11 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#12 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#13 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#14 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#15 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#16 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#17 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#18 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#19 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#20 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#21 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#22 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#23 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#24 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#25 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#26 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#27 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#28 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#29 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#30 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#31 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#32 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#33 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#34 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#35 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#36 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#37 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#38 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#39 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#40 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#41 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#42 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#43 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#44 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#45 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#46 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#47 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#48 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#49 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#50 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#51 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#52 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#53 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#54 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#55 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#56 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#57 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#58 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#59 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#60 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#61 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#62 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#63 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#64 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#65 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#66 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
#67 0x0041a1de in sem_globally_static (t=t@entry=0x801687d8) at sem.c:5075
#68 0x0041a3f4 in sem_globally_static (t=<optimized out>) at sem.c:5045
[SNIP]

event attribute not allowed on arrays

The following code leads to invalid attribute reference:

library ieee;
use ieee.std_logic_1164.all;

entity test7 is
port (
clk_i : in std_logic_vector(7 downto 0);
o : out std_logic
);
end entity test7;

architecture rtl of test7 is
begin
process (clk_i(0))
begin
if (clk_i(0)'event and clk_i(0)='1') then
o <= '1';
end if;
end process;

end architecture rtl;

lib.c:lib_find_at always converts entire path to lower case

lib.c:lib_find_at always converts the entire path to lower case resulting in errors with capital letters in the path prefix of library folders.

Recommended fix:
Maybe only the library name should be converted to lower case?

expression cannot be folded to an integer constant

ATM w/ proposed regression array4.vhd (https://gist.github.com/hiyuh/8782789), i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee ./src/nvc -a test/regress/array4.vhd
[SNIP]
** Fatal: expression cannot be folded to an integer constant
        File test/regress/array4.vhd, Line 230
      iAx : integer range 0 to cLx-1;
                               ^^^^^

above snipped errors are related record signals are already subject to issue #35.

P.S. i can reduce LOC of array4.vhd more, if required.

T_AGGREGATE not supported as actual

Component instanciation with aggregates fails:
Fatal: tree T_AGGREGATE not supporte as actual

library ieee;
use ieee.std_logic_1164.all;

entity comp2_bot is
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp2_bot is
begin
y <= x;
end architecture;

entity comp2 is
end entity;

architecture rtl of comp2 is
signal b: std_logic_vector(7 downto 0);

component comp2_bot is
    port (
        x : in std_logic_vector(7 downto 0);
        y : out std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp2_bot
    port map ( x=>x"aa", y=>b );

end architecture;

llvm-config problem under Ubuntu 13.10

Hello,

want to try your VHDL compiler, because a alternative to GHDL which is a pain to build would be nice.

I want to build nvc under Ubuntu 13.10. I've installed all the dependencies which were mentioned in the readme:

sudo apt-get install build-essential automake autoconf autoconf-archive flex \
libreadline-dev tcl-dev check llvm-dev pkg-config

When I'm running configure, I get this error:

....
checking for LLVM (engine bitreader bitwriter)... no
checking for LLVM shared library... yes
configure: error: We could not detect the llvm libraries make sure that llvm-config is on your path or specified by --with-llvm.

llvm-config exists under /usr/bin:

tmeissner@msn:~/Projects/nvc/build$ which llvm-config
/usr/bin/llvm-config

When I'm adding the --with-llvm=/usr/bin/llvm-config nothing changes, I get the same error.

So, what's the problem in this case? The installed LLVM version is 3.2

deref process label in the process itself via instance_name attribute

w/ proposed regression issueX,

entity issueX is
begin
end entity issueX;

architecture a of issueX is

begin

    p : process
    begin
        report p'instance_name;
        wait;
    end process p;

end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueX.vhd
** Error: undefined identifier P
        File test/regress/issueX.vhd, Line 11
      report p'instance_name;
             ^

direct concatenation before conversion not allowed

The following code produces the error: no composite type.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity test3 is
port(
a: in std_logic_vector(5 downto 0);
b: out unsigned (7 downto 0)
);
end entity;

architecture rtl of test3 is
signal tmp: std_logic_vector(7 downto 0);
begin
tmp<=a&"11";
--b<=unsigned(tmp); --ok
b<=unsigned(a&"11"); --error
end rtl;

elaborate top-level entity having generics and/or ports w/ their defaults

w/ proposed regression issueZ,

entity issueZ is
    generic (g : integer := 0);
    port (i : in  bit := '0');
begin
end entity issueZ;

architecture a of issueZ is
begin
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueZ.vhd
[no error]

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -e issueZ
** Fatal: top-level entity may not have generics or ports

using type conversion in actual_part of association_element in port_association_list

some coding policy restrict use of custom type in top generics/ports.
in test bench, to stub above parts, using trivial type conversion directly in actual_part is often seen, due to VHDL's strong-type language favor.

w/ proposed regression issueJ,

library ieee;
use ieee.std_logic_1164.all;

entity comp is
    generic (w : integer := 8);
    port (i : in  std_logic_vector(w-1 downto 0));
begin
end entity comp;

architecture a of comp is
begin
end architecture a;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity issueJ is
begin
end entity issueJ;

architecture a of issueJ is
    component comp is
        generic (w : integer := 8);
        port (i : in  std_logic_vector(w-1 downto 0));
    end component comp;
begin
    u : comp
    generic map (w => 8)
    port map (i => std_logic_vector(to_unsigned(0, 8)));
end architecture a;

then i got,

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -a test/regress/issueJ.vhd
# NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueJ.vhd

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -e issueJ
# NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -e issueJ
** Fatal: tree T_TYPE_CONV not supported as actual
        File test/regress/issueJ.vhd, Line 30

support two-process method

Jiri Gaisler's two-process method is one of VHDL coding style.
http://www.gaisler.com/doc/vhdl2proc.pdf
http://www.gaisler.com/doc/structdes.pdf

i usually code based on this style for over 5 years in real FPGA projects and its really nice. so, id like to make nvc supports this coding style!

ATM, w/ proposed regression tp1.vhd (https://gist.github.com/hiyuh/8781618), i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee ./src/nvc -a test/regress/tp1.vhd
** Error: sorry, records are not yet allowed as signals
        File test/regress/tp1.vhd, Line 49
     signal g : t;
     ^^^^^^^^^^^^^
** Error: sorry, records are not yet allowed as signals
        File test/regress/tp1.vhd, Line 50
     signal r : t := c;

any thoughts?

using instance_name attribute in entity_statement_part

w/ proposed issueX regression,

entity issueX is
    generic (
        g : bit := '0'
    );
begin
    assert (g = '0' or g = '1')
        report issueX'instance_name & "oops!"
        severity failure;
end entity issueX;

architecture a of issueX is
begin
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueX.vhd
** Error: object ISSUEX has no attribute INSTANCE_NAME
        File test/regress/issueX.vhd, Line 7
      report issueX'instance_name & "oops!"
             ^^^^^^^^^^^^^^^^^^^^

tcl.h is not always under tcl/.

on gentoo, tcl.h is located at /usr/include/tcl.h.
maybe, location of tcl.h is distribution specific.
could you mind to make prefix of tcl.h configurable?

compile failure w/ -Wall -Werror

after removing -Werror from Makefile.am like this:

diff --git a/src/Makefile.am b/src/Makefile.am
index 32f8aca..1f37c82 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -3,7 +3,7 @@ SUBDIRS = rt
bin_PROGRAMS = nvc
noinst_LIBRARIES = libcgen.a libnvc.a

-AM_CFLAGS = -Wall -Werror
+AM_CFLAGS = -Wall
AM_YFLAGS = -d --locations --report=all
AM_LDFLAGS = -rdynamic $(LLVM_LDFLAGS)

diff --git a/src/rt/Makefile.am b/src/rt/Makefile.am
index 11e6c8f..cd97331 100644
--- a/src/rt/Makefile.am
+++ b/src/rt/Makefile.am
@@ -1,6 +1,6 @@
noinst_LIBRARIES = libnvc-rt.a libjit.a

-AM_CFLAGS = -Wall -Werror -I$(srcdir)/..
+AM_CFLAGS = -Wall -I$(srcdir)/..

libnvc_rt_a_SOURCES = rtkern.c slave.c shell.c alloc.c vcd.c heap.c

I got some warning:

rtkern.c:286:13: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
lib.c:74:12: warning: ignoring return value of ‘realpath’, declared with attribute warn_unused_result
util.c:55:2: warning: #warning "Don't know the IP register name for your architecture!"
util.c:415:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
util.c:409:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
util.c:404:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
util.c:399:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
util.c:394:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
util.c:389:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
ident.c:137:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
ident.c:138:10: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
tree.c:1806:18: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result
tree.c:1384:12: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result
tree.c:1365:13: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result

the third warning "Don't know the IP register name for your architecture!" is cased by I'm on gentoo/~ppc.
others are trivial but they're useless.
could you mind to make -Werror optional?

invalid aggregate index bound check error

w/ proposed issueY,

entity issueY is
begin
end entity issueY;

architecture a of issueY is
begin
    p : process
        variable v : bit_vector(7 downto 0) := (others => '0');
    begin
        v(3 downto 0) := (7 downto 4 => '1');
        v(7 downto 4) := (3 downto 0 => '1');
        assert (v = (7 downto 0 => '1'));
        wait;
    end process p;
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueY.vhd
** Error: aggregate index 7 out of bounds 3 downto 0
        File test/regress/issueY.vhd, Line 10
      v(3 downto 0) := (7 downto 4 => '1');
                        ^
** Error: aggregate index 4 out of bounds 3 downto 0
        File test/regress/issueY.vhd, Line 10
      v(3 downto 0) := (7 downto 4 => '1');
                                 ^
** Error: aggregate index 3 out of bounds 7 downto 4
        File test/regress/issueY.vhd, Line 11
      v(7 downto 4) := (3 downto 0 => '1');
                        ^
** Error: aggregate index 0 out of bounds 7 downto 4
        File test/regress/issueY.vhd, Line 11
      v(7 downto 4) := (3 downto 0 => '1');
                                 ^

underscores in strings are not ignored

The following code leads to open stackdumpfile:
library IEEE;
use IEEE.std_logic_1164.all;

package test4 is
constant C0 : std_logic_vector(7 downto 0) := X"AB"; --ok
constant C1 : std_logic_vector(7 downto 0) := X"A_B"; --error

end test4;

specific overloading not possible

The overloading with selected operators leads to the error "no suitable overload":

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned."+"; -- error
--use ieee.std_logic_unsigned.all; -- ok

entity synopsys1 is
end entity;

architecture test of synopsys1 is
begin
process is
variable x, z : std_logic_vector(2 downto 0);
begin
x :="100";
z := x + 1;
wait;
end process;
end architecture;

support std.env package

VHDL-2008 has std.env package.
http://www.eda.org/fphdl/
http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_small/#env

could you mind to support std.env.{stop,finish}()?

VHDL halts simulation if all processes waits.
so sane test bench should give expected results after just "run all".
but we sometimes need to manage specific simulation time or manual simulation breakings b/c some vendor provides ton of insane library models, so calling std.env.{stop,finish}() in test bench is one of workarounds.

UPDATE: add missing env package name.

using aggregate via generic raises SIGSEGV at tree.c:1667

w/ proposed regression issueD,

entity c is
    generic (g : bit_vector := (1 downto 0 => '1'));
begin
end entity c;

architecture a of c is
begin
end architecture a;

entity issueD is
begin
end entity issueD;

architecture a of issueD is
    component c is
        generic (g : bit_vector := (1 downto 0 => '1'));
    end component c;
begin
    u : c
    generic map (g => (1 downto 0 => '1'));
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueD.vhd
Segmentation fault (core dumped)

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src gdb ./src/nvc.exe
[SNIP]
Reading symbols from /home/hiyuh/git-repos/nvc/src/nvc.exe...done.
(gdb) r -a test/regress/issueD.vhd
Starting program: /home/hiyuh/git-repos/nvc/src/nvc.exe -a test/regress/issueD.vhd
[New Thread 2108.0x618]
[New Thread 2108.0xaa8]

Program received signal SIGSEGV, Segmentation fault.
0x0043822d in tree_find_attr (t=t@entry=0x200be1b8, name=name@entry=0x200514a0, kind=kind@entry=A_STRING)
    at tree.c:1667
1667    {
(gdb) bt
#0  0x0043822d in tree_find_attr (t=t@entry=0x200be1b8, name=name@entry=0x200514a0, kind=kind@entry=A_STRING)
    at tree.c:1667
#1  0x0043be90 in tree_attr_str (t=0x200be1b8, name=0x200514a0) at tree.c:1712
#2  0x00419699 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4878
#3  0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#4  0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#5  0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#6  0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#7  0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#8  0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#9  0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#10 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#11 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#12 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#13 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#14 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#15 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#16 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#17 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#18 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#19 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#20 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#21 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#22 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#23 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#24 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#25 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#26 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#27 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#28 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#29 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#30 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#31 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#32 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#33 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#34 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#35 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#36 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#37 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#38 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#39 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#40 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#41 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#42 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#43 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#44 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#45 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#46 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#47 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#48 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#49 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#50 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#51 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#52 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#53 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#54 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#55 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#56 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#57 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#58 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#59 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#60 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#61 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#62 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#63 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#64 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#65 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
#66 0x00419747 in sem_locally_static (t=t@entry=0x20124170) at sem.c:4885
#67 0x004197f4 in sem_locally_static (t=<optimized out>) at sem.c:4944
---Type <return> to continue, or q <return> to quit---
[SNIP]

missing predefined functions returns universal_real

VHDL-1993 has following predefined functions returns universal_real, but they are missing ATM.

-- function "*" (anonymous: universal_real; anonymous: universal_integer)
-- return universal_real;
-- function "*" (anonymous: universal_integer; anonymous: universal_real)
-- return universal_real;
-- function "/" (anonymous: universal_real; anonymous: universal_integer)
-- return universal_real;

w/ proposed issueY,

entity issueY is
begin
    assert (1.0 * 1 = 1.0);
    assert (1 * 1.0 = 1.0);
    assert (1.0 / 1 = 1.0);
end entity issueY;

architecture a of issueY is
begin
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueY.vhd
** Error: no suitable overload for operator "*"(universal real, universal
          integer) return REAL
        File test/regress/issueY.vhd, Line 3
     assert (1.0 * 1 = 1.0);
             ^^^^^^^
** Error: no suitable overload for operator "*"(universal integer, universal
          real) return REAL
        File test/regress/issueY.vhd, Line 4
     assert (1 * 1.0 = 1.0);
             ^^^^^^^
** Error: no suitable overload for operator "/"(universal real, universal
          integer) return REAL
        File test/regress/issueY.vhd, Line 5
     assert (1.0 / 1 = 1.0);
             ^^^^^^^

libraries and packages not found

Usage of "use work.all" or "use libxyz.all" causes that packages or libraries are not found:

package pack0 is
constant v : bit_vector := "10";
end package;

entity pack is
end entity;

use work.all; -- ok, when line is removed
use work.pack0.all;

architecture test of pack is
begin
process is
begin
assert v = "10";
wait;
end process;
end architecture;

generic wrapping function raises SIGSEGV at src/common.c:206

sometimes generics will be wrapped into appropriated constants in their architecture.

w/ proposed regression issueA,

entity issueA is
    generic (
        L : integer range 0 to integer'high
    );
begin
end entity issueA;

architecture a of issueA is
    pure function fL (
        iDUMMY : boolean
    ) return integer is
    begin
        if (L < 1) then
            return 1;
        else
            return L;
        end if;
    end function fL;
    constant cL : integer range 1 to integer'high := fL(true);
begin
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueA.vhd
Segmentation fault (core dumped)

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src gdb ./src/nvc.exe
[SNIP]
(gdb) r -a test/regress/issueA.vhd
Starting program: /home/hiyuh/git-repos/nvc/src/nvc.exe -a test/regress/issueA.vhd
[New Thread 6996.0x1aac]
[New Thread 6996.0x1624]

Program received signal SIGSEGV, Segmentation fault.
0x00450b86 in folded_bool (t=t@entry=0x800c4dd8, b=b@entry=0x0) at common.c:206
206              *b = (tree_pos(decl) == 1);
(gdb) bt
#0  0x00450b86 in folded_bool (t=t@entry=0x800c4dd8, b=b@entry=0x0) at common.c:206
#1  0x0045ad5e in folded (t=0x800c4dd8) at eval.c:157
#2  0x0045b67a in eval_fcall (t=t@entry=0x800c4e78, v=v@entry=0x28a960) at eval.c:385
#3  0x0045cd76 in eval (fcall=0x800c4e78) at eval.c:670
#4  0x004314fc in simp_fcall (t=t@entry=0x800c4e78) at simp.c:94
#5  0x00433dad in simp_tree (t=0x800c4e78, context=0x0) at simp.c:748
#6  0x0043c091 in tree_rewrite_aux (t=0x800c4e78, ctx=ctx@entry=0x28aafc) at tree.c:1814
#7  0x0043c1f6 in tree_rewrite_aux (t=0x800c4ef0, ctx=ctx@entry=0x28aafc) at tree.c:1771
#8  0x0043bf55 in tree_rewrite_aux (t=t@entry=0x800c4f38, ctx=ctx@entry=0x28aafc) at tree.c:1776
#9  0x0043c31d in tree_rewrite (t=t@entry=0x800c4f38, fn=fn@entry=0x433bc0 <simp_tree>, context=context@entry=0x0)
    at tree.c:1836
#10 0x00433f1d in simplify (top=0x800c4f38) at simp.c:786
#11 0x00401951 in analyse (argc=argc@entry=2, argv=0x28ac00) at nvc.c:120
#12 0x004ab40d in main (argc=2, argv=<optimized out>) at nvc.c:713
[SNIP]

using packaged constant via packaged function produces undefined reference

w/ proposed regression issueI,

package p is
    pure function f(
        i : boolean
    ) return integer;
end package p;

package body p is
    pure function f(
        i : boolean
    ) return integer is
    begin
        if (i = false) then
            return 0;
        else
            return 1;
        end if;
    end function f;
end package body p;

use work.p.all;
package q is
    constant d : integer := f(true) + 1;
end package q;

package body q is
end package body q;

use work.q.all;
entity issueI is
begin
    assert (d = 2);
end entity issueI;

architecture a of issueI is
begin
end architecture a;

then i got,

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -a test/regress/issueI.vhd
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueI.vhd

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh --codegen p
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc --codegen p
/usr/bin/opt -O2 -o /home/hiyuh/git-repos/nvc/work/_WORK.P-body.bc /home/hiyuh/git-repos/nvc/work/_WORK.P-body.bc
/usr/bin/llc -relocation-model=pic /home/hiyuh/git-repos/nvc/work/_WORK.P-body.bc
/usr/bin/gcc -shared -Wl,--export-all-symbols -Wl,--out-implib=/home/hiyuh/git-repos/nvc/work/_WORK.P-body.a -o /home/hiyuh/git-repos/nvc/work/_WORK.P-body.so /home/hiyuh/git-repos/nvc/work/_WORK.P-body.s -L./src -lnvcimp

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh --codegen q
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc --codegen q
/usr/bin/opt -O2 -o /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.bc /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.bc
/usr/bin/llc -relocation-model=pic /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.bc
/usr/bin/gcc -shared -Wl,--export-all-symbols -Wl,--out-implib=/home/hiyuh/git-repos/nvc/work/_WORK.Q-body.a -o /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.so /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.s -L./src -lnvcimp /home/hiyuh/git-repos/nvc/work/_WORK.P-body.a

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -e issueI
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -e issueI
/usr/bin/opt -O2 -o /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.final.bc /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.elab.bc

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -r issueI
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -r issueI
LLVM ERROR: Could not resolve external global address: WORK.Q.D

hiyuh@lynx ~/git-repos/nvc
$ ./tools/nvc-wrapper.sh -e --native issueI
NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -e --native issueI
/usr/bin/opt -O2 -o /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.final.bc /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.elab.bc
/usr/bin/llc -relocation-model=pic /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.final.bc
/usr/bin/gcc -shared -Wl,--export-all-symbols -Wl,--out-implib=/home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.elab.a -o /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.final.so /home/hiyuh/git-repos/nvc/work/_WORK.ISSUEI.final.s -L./src -lnvcimp /home/hiyuh/git-repos/nvc/work/_WORK.P-body.a /home/hiyuh/git-repos/nvc/work/_WORK.Q-body.a
/tmp/ccsCnK35.o:fake:(.text+0x5c): undefined reference to `WORK.Q.D'
collect2: error: ld returned 1 exit status
** Fatal: /usr/bin/gcc failed with status 256

NOTE: tools/nvc-wrapper.sh is my lazy wrapper script, echos some commands and eval them, you can found here. https://gist.github.com/hiyuh/9639531

IMHO, it looks similar scope problem as reported at issue #53.

port not found at component instanciation

Swapping of the order of the ports leads to: PORT Y not found in entity

library ieee;
use ieee.std_logic_1164.all;

entity comp4_bot is
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;

architecture rtl of comp4_bot is
begin
y <= x;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity comp4 is
end entity;

architecture rtl of comp4 is
signal b: std_logic_vector(7 downto 0);

component comp4_bot is
    port (
        y : out std_logic_vector(7 downto 0);
        x : in std_logic_vector(7 downto 0) );
end component;

begin

c1: component comp4_bot
    port map ( x=>x"aa", y=>b );

end architecture;

Error at elaboration stage if instanciating with bit constants

The following code leads at elaborating to the error:
assertation false failed: file elab.c, line 147, function: rewrite ports

entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;

architecture test of bitand is
begin
z <= x and y;
end architecture;

entity elab6 is
end entity;

architecture test of elab6 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
x1<='1';
wait;
end process;
end architecture;

Surprisingly the commented version with y=>y1 works.

read and write in std.textio not implemented

The following reports failure unimplemented:
library STD;
use STD.TEXTIO.all;

entity tbtextio is
end tbtextio;

architecture behave of tbtextio is
file strfile: text;
begin
gendata: process
variable svar,sdummy: string(1 to 1);
variable file_line: line;
variable dummy: boolean;
begin
file_open(strfile,"test.txt",READ_MODE);
while not endfile(strfile) loop
readline(strfile,file_line);
read(file_line,svar,dummy);
end loop;
file_close(strfile);
end process;

end behave;

porting problem triggered by gcc include search order

maybe, you known I'm now porting nvc to cygwin on my fork.
and I'd like to ask you too about this problem I encounter.

http://cygwin.com/ml/cygwin/2012-02/msg00459.html

this problem is that:

src/rt/slave.c is coded to include poll.h
gcc picks /usr/include/poll.h
/usr/include/poll.h is coded to include sys/poll.h
gcc picks /usr/include/sys/poll.h
/usr/include/sys/poll.h is coded to include signal.h
gcc picks src/rt/signal.h, not /usr/include/signal.h

I rather hesitate to rename src/rt/signal.h for this stupid problem.
you have any idea?

Do not use eptr after free(tmp).

please do git cherry-pick. :)

hiyuh@316782c

make ease to use foreign attributes

NVC foreign attribute looks working really nice.
https://mail.gna.org/public/ghdl-discuss/2014-02/msg00068.html

but linking users' non-VHDL objects requires a bit cryptic SYSTEM_CC commands, i guess.
could you mind to add sane options for this use?

concatenation error

The following code leads to the analysis error "ambigous use of enumeration literal '1'":

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity test is
end entity;
architecture rtl of test is
begin
process is
variable x: std_logic_vector(4 downto 0);
variable y: integer range 127 downto 0;
begin
y := conv_integer(unsigned(x&'0'&'1'));
wait;
end process;
end architecture;

using instance_name attribute in packaged function

proposed regression issueX.vhd is reduced from my real code,

library ieee;
use ieee.std_logic_1164.all;

package p is
    function f (i : std_logic) return integer;
end package p;

package body p is
    function f (i : std_logic) return integer is
    begin
        case i is
            when '0'    => return 0;
            when '1'    => return 1;
            when others =>
                assert (i = '0' or i = '1')
                    report f'instance_name & "oops!"
                    severity warning;
                return 0;
        end case;
    end function f;
end package body p;

library ieee;
use ieee.std_logic_1164.all;
use work.p.all;

entity issueX is
begin
end entity issueX;

architecture a of issueX is
begin
    assert (f('X') = 0);
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee NVC_CYG_LIB=./src ./src/nvc.exe -a test/regress/issueX.vhd
assertion "zero_arg_fn || (tree_kind(next) == T_ENUM_LIT)" failed: file "sem.c", line 4151, function: sem_check_ref
Aborted (core dumped)

regress/ieee4.vhd fails with SIGSEGV

regress/ieee4.vhd fails with SIGSEGV inside the CORDIC function.

It seems the global pointer to the TWO_AT_MINUS array is null due to that the IEEE.MATH_REAL-body_reset function has not been executed (verified with gdb).

The reset function fails to run because jit.c:jit_search_loaded_syms mangles the name IEEE.MATH_REAL-body_reset into IEEE.MATH_REAL_2D_body_reset which is not present in the .so-file unlike the unmangled name.

nm lib/ieee/ieee/_IEEE.MATH_REAL-body.so | grep reset
00000000000046f0 T IEEE.MATH_REAL-body_reset

undefined port identifier in entity_statement_part

w/ proposed regression issueX,

entity c is
    port (i : in bit);
begin
    assert (i = '0') report "not '0'" severity note;
    assert (i = '1') report "not '1'" severity note;
end entity c;

architecture a of c is
begin
end architecture a;

entity issueX is
begin
end entity issueX;

architecture a of issueX is
    component c is
        port (i : in bit);
    end component c;
begin
    u0 : c port map (i => '0');
    u1 : c port map (i => '1');
end architecture a;

then i got,

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc -a test/regress/issueX.vhd
** Error: undefined identifier I
        File test/regress/issueX.vhd, Line 4
     assert (i = '0') report "not '0'" severity note;
             ^
** Error: undefined identifier I
        File test/regress/issueX.vhd, Line 5
     assert (i = '1') report "not '1'" severity note;
             ^

Failed in compiling in NetRunner 13.06 (Ubuntu)

Have no idea about the dependencies.

➜  nvc git:(master) ./autogen.sh 
configure.ac:61: error: possibly undefined macro: AC_WARN
      If this token and others are legitimate, please use m4_pattern_allow.
      See the Autoconf documentation.
autoreconf: /usr/bin/autoconf failed with exit status: 1

Feature request: VHPI support

A foreign language interface opens up significant possibilities for advanced verification. VHPI is now part of the IEEE 1076 standard and is therefore the obvious candidate for an interface.

As far as I am aware, there are currently no free simulators with VHPI support.

analyze fails b/c memory exhausted

vendors often provide their models as structured in specific device primitives to hide their crappy IP from users then it becomes very large, like xilinx coregen sometimes generates such models even if its project sets preferred simulation model to behavioral, following is an over 100k LOC example, as its file name tells clearly, it is core of FFT.

$ wc -l XFFT.vhd
118120 XFFT.vhd

NVC looks having unisim build, so just tried to analyze w/ it results simply memory exhausted.

$ NVC_LIBPATH=./lib/std:./lib/ieee:./lib/nvc NVC_CYG_LIB=./src ./src/nvc --std=1993 -a --prefer-explicit XFFT.vhd
** Error: memory exhausted
        File [SNIP]/XFFT.vhd, Line 10053
      signal blk0000123a_blk0000123b_sig00002d2a : STD_LOGIC;
                                                            ^

any thoughts?

constant propagation from packages

The following code leads to assertation tree_kind(decl) ==T_VAR_DECL failed during
elaboration.

package pack is
constant results : bit_vector(1 downto 0):="11";
end package;

use work.pack.all;
entity const3 is
end entity;
architecture test of const3 is
signal bv: bit_vector(1 downto 0);
begin
bv<=results;
end architecture;

"make check" fails at "fact"

I just got:

fact : *** glibc detected *** /home/hiyuh/git-repos/nvc/src/nvc: double free or corruption (out): 0x107dc748 ***

due to GitHub Flavored Markdown does not allow to me to paste raw check log, I'd have to snip backtrace and memory map dump after above message. If you interested, I can send you the log via e-mail or so.

multiple constant concatenation

The following code leads in the analysis to "5 main nvc2072 open stackdumpfile".
library IEEE;
use IEEE.std_logic_1164.all;

package test2 is
constant C0 : std_logic_vector(1 downto 0) := '0'&'1'; --error
-- constant C0 : std_logic_vector(1 downto 0) := "01"; --ok
constant C1 : std_logic_vector(2 downto 0) := C0&'1';
end test2;

usage of generic parameter in combination with range not possible

The following code leads to "item->tree!=Null":

entity test6 is

generic (CID : natural := 2 );
port (
ID: out natural range 1 to CID
--ID: out natural range 1 to 2 --ok
);
end test6;

second read call from std.textio fails

The second read fails (previous data read):

entity textio3 is
end entity;

use std.textio.all;

architecture test of textio3 is
begin

process is
    file tmp      : text;
    variable l    : line;
    variable str  : string(1 to 5);
    variable good : boolean;
begin
    file_open(tmp, "tmp.txt", WRITE_MODE);
    write(l, string'("hello"));
    writeline(tmp, l);
    write(l, string'("world"));
    writeline(tmp, l);
    file_close(tmp);
    file_open(tmp, "tmp.txt", READ_MODE);
    readline(tmp, l);
    read(l, str);
    assert str = "hello" report "hello fails";
    readline(tmp, l);
    read(l, str,good);
    assert str = "world" report "world fails:"&str;
    file_close(tmp);
    wait;
end process;

end architecture;

temp buffers

im pondering followings about temp buffers in src/.

$ git log -n 1
commit e77d021827b7c7079e41cd45e1f61f21dac386b9
Merge: 0ea04df 0448366
Author: Nick Gasson <[email protected]>
Date:   Tue Jan 21 12:55:04 2014 -0800

    Merge pull request #27 from hiyuh/nosignal

    NO_STACK_TRACE for cygwin

$ find src/ -name '*.[chly]' -and -not -name 'lexer.c' -and -not -name 'parse.c' \
    | xargs grep -n -e '[a-zA-Z0-9_]\+ [a-zA-Z0-9_]\+*\[[0-9]\+\]'
src/bounds.c:647:         char buf[1024];
src/cgen.c:376:   static char buf[1024];
src/cgen.c:539:   LLVMValueRef params[1][3] = { { left, right, kind } };
src/cgen.c:1187:   static char name[64];
src/cgen.c:1579:      char buf[256];
src/cgen.c:3347:      LLVMValueRef dims[1][3] = {
src/cgen.c:4944:   char name[256];
src/cgen.c:5087:   char state_name[256];
src/cgen.c:5181:   char name[256];
src/cgen.c:5253:         char buf[256];
src/cgen.c:5262:         char buf[256];
src/cgen.c:5272:      char buf[256];
src/cgen.c:5622:   char name[128];
src/cgen.c:6256:   char fname[256];
src/common.c:69:   char name[64];
src/elab.c:933:      tree_t formals[1] = { genvar };
src/elab.c:934:      tree_t actuals[1] = { get_int_lit(genvar, i) };
src/group.c:399:   char name[256];
src/lib.c:324:         char buf[2048];
src/link.c:86:   char so_name[256];
src/link.c:366:   char deps_name[256];
src/link.c:389:   char tmp[128] = "";
src/link.c:456:   char name[128];
src/nvc.c:388:      char tmp[256];
src/parse.y:2754:   char buf[128];
src/rt/cover.c:213:         char buf[1024];
src/rt/cover.c:376:   static char buf[256];
src/rt/cover.c:430:   char buf[256];
src/rt/cover.c:455:   static char buf[256];
src/rt/cover.c:475:   char buf[256];
src/rt/cover.c:523:   char dir[256];
src/rt/cover.c:537:   char buf[1024];
src/rt/fst.c:92:   char buf[128];
src/rt/jit.c:89:   char dlname[1024];
src/rt/jit.c:168:   char deps_name[256];
src/rt/jit.c:207:   char bc_fname[64], so_fname[64];;
src/rt/netdb.c:26:   char name[256];
src/rt/pprint.c:99:   static char buf[1024];
src/rt/rtkern.c:524:   char suffix[128] = "";
src/rt/rtkern.c:969:   char buf[64];
src/rt/rtkern.c:1091:         int8_t args[2] = { i, j };
src/rt/rtkern.c:1101:      int8_t args[1] = { i };
src/rt/rtkern.c:1286:   char buf[128];
src/rt/rtkern.c:1506:         int driving[2] = { p0[j], p1[j] };
src/rt/rtkern.c:1669:   char buf[2048];
src/rt/rtkern.c:2134:   uint64_t value[1];
src/rt/rtkern.c:2137:   uint64_t last[1];
src/rt/rtkern.c:2174:      char buf[256];
src/rt/shell.c:61:   char buf[1024];
src/rt/slave.c:116:   int socks[2];
src/rt/slave.h:65:   uint64_t values[0];
src/rt/vcd.c:97:   char tmbuf[64];
src/rt/wave.c:71:   char line[1024];
src/rt/wave.c:82:      char glob[1024];
src/rt/wave.c:96:   char buf[256];
src/sem.c:388:   static char buf[1024];
src/sem.c:426:   char argname[16];
src/sem.c:3195:      char buf[1024];
src/sem.c:3225:      char fn[512];
src/sem.c:3320:      char buf[1024];
src/sem.c:3334:      char fn[512];
src/sem.c:4402:      char buf[32];
src/type.c:332:      char buf[128];
src/util.c:429:   char buf[80];
src/util.c:576:   int mib[4];
src/util.c:594:      char buf[1024];
src/util.c:656:   char exe[256];
src/util.c:660:   char pid[16];

purge temp buffers w/ hard-coded length
use standard functions, malloc bits or bgw-gc?
add GC for temp buffers
use standard functions, malloc bits or bdw-gc?
add built-in memory checker
valgrind has some issues b/c libc optimized functions on some arch, IIRC.
efence is not thread-safe.
DUMA looks thread-safe.
if bdw-gc is used for above things, it looks best choice to me (of course, other than adding new lib dep), if the modified code has execution speed issue.

any thoughts?

update from first post:

fix a markdown typo for line breaking.
add list of temp buffers.

nickg / nvc Goto Github PK

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