Comments (6)
Fixed by b312d94
from nvc.
Thanks a lot, the issue is fixed, I suceeded now to move to the elaboration stage. Unfortunately components are not allowed in elaboration (regress/comp1.vhd: instanciating components is not supported yet) and my complete
design is build up with components and not with entities..
from nvc.
Unfortunately that's not implemented yet. Hopefully I'll add it soon.
from nvc.
That would be very helpful. A less important point: omiting outputs at instanciating is not allowed. That would be a nice option to reduce typing.
from nvc.
Should be able to leave outputs unconnected now
from nvc.
I've added some very basic support for component instantiation. Might be worth having another go?
from nvc.
Related Issues (20)
- Support merging covdbs with different top-level architectures HOT 3
- Record Resolution and Upgrade to version 1.11.2 HOT 12
- Sensitivity lists and aggregates HOT 6
- aggregate and array directions when the aggregate is in an expression HOT 5
- Aggregates and VHDL-2008 stuff HOT 5
- Guarded blocks HOT 1
- invalid type kind T_ARRAY in range_of a bunch of addresses HOT 2
- ** Fatal: cannot rewrite generic DIM to tree kind T_FCALL
- Inconsistent documentation for generic
- Working directory in search paths for libraries HOT 7
- PSL - an option to treat analyze errors as warnings HOT 4
- Slicing type conversion HOT 2
- How to compile vendor libraries with different standard HOT 4
- Analyzing vhdl file results in 'Fatal: Write to object in frozen arena' HOT 2
- What does missing vcode unit during elaboration mean HOT 3
- Caught signal 11 (SEGV_MAPERR) HOT 2
- Rebuild std libraries on compile HOT 1
- fatal: invalid type kind T_ARRAY in range_of
- ** Fatal: dst argument to map signal is not a signal HOT 2
- Simulation of large design ends with: Fatal: missing variable for generic X in Y HOT 4
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from nvc.