Design, Implementation and Simulation of 6T SRAM Cell under Mixed Signal SOC Design Marathon using eSim & SKY130 by FOSSEE & IITB with Mr. Kunal Ghosh

• Introduction
• Reference Circuit Diagram
• Circuit Details
• Designing Steps
• Open Source Tools Used
• Verilog Code
• Schematics
• Netlist
• Output Waveforms
• Author
• Acknowledgements
• References

eSim : It is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD. For more details refer: https://esim.fossee.in/home

NgSpice : It is an Open Source Software for Spice Simulations. For more details refer: http://ngspice.sourceforge.net/docs.html

Makerchip : It is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. For more details refer: https://www.makerchip.com/

Verilator : It is a tool which converts Verilog code to C++ objects. For more details refer: https://www.veripool.org/verilator/

1. Kunal Ghosh (Co-Founder, VLSI System Design Pvt. Ltd.)
2. FOSSEE, IIT Bombay
3. Sumanto Kar (eSim Team, FOSSEE, IIT Bombay)