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4.0 3.0 1.0 174.43 MB

MPW6 submission from the Zero to ASIC Course

Home Page: https://zerotoasiccourse.com/

License: Apache License 2.0

Makefile 0.04% Tcl 0.02% C 0.07% Verilog 99.87%

asic efabless sky130 verilog mpw6

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zero_to_asic_mpw6's Issues

Missing verilog/rtl/user_project_includes.v

@mattvenn
I am trying to add to your project here: https://github.com/The-OpenROAD-Project/OpenLane-MPW-CI

But its missing user_project_includes.v and throws error during synthesis.

Can you please update the missing files?

1. Executing Verilog-2005 frontend: /openlane/designs/mpw6_zero_to_asic/openlane/user_project_wrapper/../../caravel/verilog/rtl/defines.v
ERROR: Can't open input file `/openlane/designs/mpw6_zero_to_asic/openlane/user_project_wrapper/../../verilog/rtl/user_project_includes.v' for reading: No such file or directory
child process exited abnormally

Missing RTL for wrapped_scan_test

Sorry to knock your door again.
Missing following include file in rtl directory.

zero_to_asic_mpw6/verilog/rtl/user_project_includes.v

Line 26 in 0bea000

`include "wrapped_scan_test/wrapper.v" // 13

Thanks.

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