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General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board

Verilog 87.57% Stata 8.62% Python 3.63% Mathematica 0.18%

architecture cpu cpu-architecture de0-nano fpga hdl verilog

ev21g1's Introduction

👋 Hello! I'm Lucas

Hello! I'm Lucas, an Electronics Engineer from the ITBA (Instituto Tecnológico de Buenos Aires). With a versatile background in hardware, software, and firmware, I've had the opportunity to work on various projects. My expertise lies in developing for embedded devices like FPGAs and microcontrollers, where I've utilized languages such as C and C++. Additionally, I'm skilled in capturing schematics and designing PCB layouts using professional tools like Altium Designer.

I'm passionate about learning new skills and solving problems using technology, even more, when it represents a challenge.

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ev21g1's Issues

Docs - Include processor documentation

Port registers bank uses the negative edge of the clock to latch the input port of the processor

This is not correct, mainly because how each stage is driven by the clocks sent from the pipeline. When I created the register bank, I used the negative edge because I had in mind the clock scheme of a processor with no pipeline.

Processors run tests codes

The issue is different form #21, this can be closed if there are several assembly programs prepared and already tested on the FPGA.

Implementation - Clock generation and distribution (Pipeline)

For the pipeline to work, the clock sent to each sequential block in the microarchitecture requires to be out of phase to avoid stability problems. The positive edge of the clock sent to each part of the hardware requires to be separated in time more than the hold time of the latches (among other key units).

Negate the IFU clock outside the module, so it is clearer in the CPU architecture it works with negative edge

Pipeline - Bus access dependency control units

Compiler - Add subroutine top level reached warning

Design - Assign type and opcode fields in the instruction set

Implementation - Micro-Operation ROM (Decoding)

Needs #4

Implementation - ALU

Add an instruction to perform an AND between Register and Constant value

An OR has already been implemented to allow 32 bit constants. Adding an AND would improve bit wise capabilities of the processor.

Implementation - Program Memory

Erase program_memory from the project

PSR was left outside the register bank, ¿is this correct?

Verify if the memory read and write operations are correctly defined for the architecture

Does it need to generate some hold/stall signal to await for memory results?
Are we expecting for the memory to answer in a machine cycle?

Implementation - IFU

Memory operations dependency between operand and retire

Testing - Hardware test of output and input ports

Using some version of the processor, use a simple program to test if the inputs and outputs of the FPGA are correctly driven. Also, verify correct assignment of the pinout of the processor.

Report conventions/glossary

No words should be said as if the reader knows their meaning or is familiar with the terminology. Create a glossary of conventions for each word used, even if it's quite simple.

Implementation - Data Path

The data path refers to the combination of the ALU, the Shifter, the Register Bank, and some other functional blocks used mainly to operate the last three stages of the processor pipeline.

Boot sequence

Although it can be quite simple, we need to define a boot sequence (i think...). For example, ¿is there any reset signal? ¿what is the reset value for the Program Counter?

Design - Draw schemes to clarify the explanation of the reference manual

Connect input and output ports to the FPGA pinout available (IO Interface)

Design - VGA configurable resolution, ¿is it possible?

Docs - Timing diagram (Pipeline)

A timing diagram showing how a machine cycle runs throughout the stages of the processor could be really helpful and useful to ensure we are all in the same page.

Pipeline - Register dependency control units

Testing - Memory blocks for program and data

Hardcode an assembly program in the program memory and test if the processor runs correctly
Write and read memory variables to see if the data memory works correctly

Docs - Add ROM (program memory) space

Testing - Hardware test of VGA module

Can we test the VGA module with a monitor, or do we need some electrical interface between the monitor and the FPGA?
Decide whether to test using simulation or hardware
Test the VGA module

Implementation - Fetch Stage

Testing - Prepare machine code to be run in the processor

We will need to have already prepared programs to run in the processor, maybe an assembler basic compiler could be developed in Python to make it easier for us, because we could create programs using Assembler Language. If so, a recommend creating a directory tools/ for the toolchain.

MIR (Micro Instruction ROM)
MIR Format N° 1
MIR Format N° 2
Instruction Decoder