Comments (2)
Kammann123
commented on June 26, 2024
Generate a hold or stall signal when a dependency between consecutive instructions is detected,
- If MAR and MDR registers are being used in consecutive instructions
- If an instruction uses as operand the result of the immediately past instruction
- Conditional branch, stop the conditional branch instruction in the decode stage until the result is ready (the instruction evaluating a condition is in the retire stage)
- Unconditional branch, ¿something to take care of?
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matifrancois
commented on June 26, 2024
The first 2 items are ready and tested
The last 2 items are in process
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Related Issues (20)
- Data memory dependency problem not being taken care of
- Add an instruction to perform an AND between Register and Constant value
- Data memory should respond in the execute stage not in the retire stage
- Data and program memory clock management
- Erase program_memory from the project
- Negate the IFU clock outside the module, so it is clearer in the CPU architecture it works with negative edge
- CPU Reset Strategy
- Memory operations dependency between operand and retire
- Testing - Jump and branch instructions HOT 1
- Compiler - Add support for ORG directives
- Compiler - Add labels
- Compiler - Automatic calculation of branch and jump offset using labels
- Docs - Add ROM (program memory) space
- Compiler - Add subroutine top level reached warning
- Do not write address and data buses when not performing memory operation
- Pipeline - Register dependency control units
- Pipeline - Bus access dependency control units
- Pipeline - Jump and branch control units
- Pipeline - Define NOP for instructions
- Pipeline - Define NOP for microinstruction
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